Abstract: In a verification supporting apparatus, when an obtaining unit obtains a verification scenario, a substituting unit substitutes an undefined value for a variable value in the verification scenario. A first executing unit executes a logic simulation using an input pattern. From a result of the logic simulation, a determining unit generates code-coverage upper-limit information. A setting unit sets input patterns by giving an arbitrary logic value to the variable value. A second executing unit executes a logic simulation using the input patterns set. A generating unit generates code coverage from the input patterns set. A calculating unit calculates a level of achievement of the code coverage with respect to the code-coverage upper-limit information.

Abstract: A logical verification device includes an input unit, a generator, an input constraint information calculator, an output constraint information calculator, an input/output constraint information calculator, a determining unit, and a logic verifying unit. The input unit inputs hardware description information and interface specification description information concerning a communication procedure of a hardware module. The generator generates a finite state machine model concerning a status transition of signals input to and output from the hardware module, based on the interface specification description information. The input constraint information calculator calculates input constraint information using the generated finite state machine model.

Abstract: First, a graph of a set of transition sequences representing the property to be satisfied by a finite state machine which is a model of a logical device. Then, a node to be processed is selected from the graph, and one of the branches connected to the node is selected. A mapping operation is performed on a set of states of the node on the starting side of the selected branch, and the result is added to the set of states of the node on the ending side. As a result of the mapping operation, it is determined whether or not the set of states which satisfies the target property has been obtained, that is, whether or not an example of a transition sequence has been successfully detected. If it has been successfully detected, then it is assumed that there is a transition sequence, the process terminates. If it has not been successfully detected, then it is determined whether or not there is an unprocessed branch connected to the node. If yes, the above described process is repeated.

Abstract: Information of definitions on interface specifications capable of expressing parallel behaviors is stored in a computer-readable storage medium while amounts of information are reduced. The present invention comprises: a first identifier region for storing, as a first set of ports, combination patterns of signal values that respective ports of a first set of ports are capable of assuming; a second identifier region for storing, as a second set of ports, combination patterns of signal values that respective ports of a second set of ports are capable of assuming; and a third identifier region for storing, as a third set of ports, functions of a circuit module defined as combinations of first identifiers and second identifiers, wherein the third identifiers include codes (par) indicating that starting order of combination patterns corresponding to the first identifiers and combination patterns corresponding to the second identifiers are undefined.

Abstract: A verification apparatus which verifies whether or not a finite state machine indicating the operation of a synchronous sequential machine satisfies the property indicating the functional specification repeats the image computation in the M and the computation of a set product by q starting with the state set p when the finite state machine M, the subset q of the state of the M, and the subset p of the q are given; and checks the relation of the state set of the computation process. As a result, it can be determined, starting with a certain state in the p, whether or not a state transition path which eternally does not exceed the q exists.

Abstract: First, an initial operation model M.sub.0 of a pipeline is configured according to the pipeline configuration of a processor and the specification information about an instruction executed by the processor. Then, the number of the states of the initial operation model M.sub.0 is minimized to configure an operation model M. Based on the operation model M and a test state set H, listed are test instruction strings for the process in which the state of the operation model M indicates a transition from a predetermined input state to any of the test states contained in the test state set H without an occurrence of a conflict in the operation model M. A next time state, reached after the state of the operation model M has reached the test state of the test instruction string, is calculated and the next time state is input as a new input state to a test instruction string listing unit.

Abstract: Specification information is input about a pipeline process of a plurality of instructions to be executed by a pipeline processor. Each pipeline stage of the instructions can have a different configuration, and the processor can have a plurality of similar pipeline stages. The pipeline has a plurality of pipeline stages each having a different clock number. When the specification information is entered, listed are a plurality of states in which hazards are caused among a plurality of instructions executed by the processor. An instruction string is generated corresponding to each of the listed states. Thus, the operation of the pipeline control mechanism can be verified with high reliability for various processors such as a processor which supports an instruction having different pipeline stage configurations, a processor provided with a plurality of similar pipeline stages, etc.