Patents by Inventor Hiroaki Kameyama

Hiroaki Kameyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136744
    Abstract: A connector comprises a housing, a terminal and a shell. The terminal has a held portion held by the housing, a first portion extending rearward from the held portion and a second portion extending forward from the held portion. The first portion has a connectable portion configured to be connected to a first object. The second portion has a resiliently deformable support portion and a contact portion supported by the support portion. The contact portion is pressed against a second object when the connector is fixed on the second object. The shell has a first upper plate and a second upper plate which is located below the first upper plate. The first upper plate covers the first portion of the terminal from above. The second upper plate covers the second portion of the terminal from above.
    Type: Application
    Filed: September 5, 2023
    Publication date: April 25, 2024
    Applicant: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
    Inventors: Yuichi SAITO, Yukitaka TANAKA, Gota KAMEYAMA, Yukiko SATO, Hiroaki KURIBAYASHI
  • Patent number: 11770630
    Abstract: A photoelectric conversion apparatus includes a second substrate including a signal processing circuit configured to perform signal processing using machine learning on a signal output from the first substrate. The second substrate is disposed on the first substrate in a multilayer structure. The signal processing circuit is so disposed to overlap with a pixel array but not overlap with a light-shielded pixel area as seen in a plan view.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: September 26, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masaki Sato, Masahiro Kobayashi, Tatsuya Ryoki, Kohichi Nakamura, Daisuke Kobayashi, Hiroaki Kameyama, Yasuhiro Oguro
  • Publication number: 20230297940
    Abstract: A storage medium storing an information processing program that causes a computer to execute a process that includes acquiring a first candidate group that includes candidates of operating routes of each of a plurality of mobile bodies; acquiring a second candidate group that includes candidates of delivery routes of each of packages, the delivery routes being combinations of candidates of operating routes; setting a function that uses a first variable that indicates whether to select each of the candidates included in the first candidate group and a second variable that indicates whether to select each of the candidates included in the second candidate group; determining operation and delivery routes so as to minimize the value specified by the function under a constraint that candidates of operating routes included in the combination of selected candidates of the delivery routes according to the second variable, are selected according to the first variable.
    Type: Application
    Filed: December 13, 2022
    Publication date: September 21, 2023
    Applicant: Fujitsu Limited
    Inventors: Hiroshi IKEDA, HIROAKI KAMEYAMA
  • Publication number: 20230276147
    Abstract: A photoelectric conversion device includes a pixel array having aperture pixels arranged so as to form rows and columns, signal lines arranged in the pixel array so as to allow readout of signals from the aperture pixels, current sources connected to the signal lines, a first voltage supply line configured to supply a first reference voltage to the aperture pixels, a first pad connected to the first voltage supply line, a bias circuit configured to supply a bias voltage to the current sources, a second voltage supply line electrically separated from the first voltage supply line, and configured to supply a second reference voltage to the bias circuit, and a second pad connected to the second voltage supply line.
    Type: Application
    Filed: February 23, 2023
    Publication date: August 31, 2023
    Inventors: YU ARISHIMA, KOICHIRO IWATA, HIROAKI KAMEYAMA, MASAKI SATO
  • Patent number: 11627269
    Abstract: An analog-to-digital conversion circuit includes a comparator circuit configured to perform processing of comparison between an analog signal and a ramp signal, and a counter configured to perform count processing in parallel with the comparison processing by the comparator circuit. The analog-to-digital conversion circuit acquires digital data, which is a count value corresponding to the comparison processing, and subjects the analog signal to analog-to-digital conversion. A period from the start to the end of the analog-to-digital conversion of the one analog signal includes a first period and a second period following the first period. The first and the second periods are switched based on an output of the counter. The count processing is performed at a high speed during the first period and performed at a low speed during the second period.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: April 11, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kohichi Nakamura, Hiroaki Kameyama, Koichiro Iwata, Yu Arishima
  • Patent number: 11575868
    Abstract: A photoelectric conversion apparatus includes a control unit configured to change a voltage of an input node from a first voltage toward a predetermined voltage during a predetermined time period after the voltage of the input node changes to the first voltage and before the voltage of the input node changes to a second voltage. A method of driving the photoelectric conversion apparatus includes controlling changing of the voltage of the input node from the first voltage toward the predetermined voltage during the predetermined time period.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: February 7, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hiroaki Kameyama, Seiichirou Sakai, Kazuo Yamazaki
  • Patent number: 11552647
    Abstract: A ramp signal output circuit includes a first reference current source transistor to which a current is supplied from a current source, a first line connecting a gate of the first reference current source transistor and a gate of a first current source transistor, a branch point where a second line branches from the first line, a first ramp signal generation unit connected to the first current source transistor, and a second ramp signal generation unit connected to a second current source transistor, wherein the second line is connected to a gate of the second current source transistor.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: January 10, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Seiichirou Sakai, Kazuo Yamazaki, Hiroaki Kameyama
  • Publication number: 20220353448
    Abstract: A plurality of comparison circuits each including a first terminal for inputting a first analog signal and a second analog signal and a second terminal connected to a wiring for transmission of a ramp signal A first operation changes an electric potential of the wiring from a predetermined electric potential to a first electric potential to cause at least one of the plurality of comparison circuits to retain a first offset. A second operation, after the first operation, converts the first analog signal into a digital signal. A third operation, after the second operation, changes the electric potential of the wiring to an electric potential included in a range of from the predetermined electric potential to the first electric potential. A fourth operation, after the third operation, converts the second analog signal into a digital signal.
    Type: Application
    Filed: April 25, 2022
    Publication date: November 3, 2022
    Inventors: Hideaki Takada, Hiroaki Kameyama, Masanori Ogura, Makiko Saito, Takuya Hara
  • Publication number: 20220247948
    Abstract: A photoelectric conversion apparatus includes a second substrate including a signal processing circuit configured to perform signal processing using machine learning on a signal output from the first substrate. The second substrate is disposed on the first substrate in a multilayer structure. The signal processing circuit is so disposed to overlap with a pixel array but not overlap with a light-shielded pixel area as seen in a plan view.
    Type: Application
    Filed: February 1, 2022
    Publication date: August 4, 2022
    Inventors: Masaki Sato, Masahiro Kobayashi, Tatsuya Ryoki, Kohichi Nakamura, Daisuke Kobayashi, Hiroaki Kameyama, Yasuhiro Oguro
  • Publication number: 20220141414
    Abstract: An analog-to-digital conversion circuit includes a comparator circuit configured to perform processing of comparison between an analog signal and a ramp signal, and a counter configured to perform count processing in parallel with the comparison processing by the comparator circuit. The analog-to-digital conversion circuit acquires digital data, which is a count value corresponding to the comparison processing, and subjects the analog signal to analog-to-digital conversion. A period from the start to the end of the analog-to-digital conversion of the one analog signal includes a first period and a second period following the first period. The first and the second periods are switched based on an output of the counter. The count processing is performed at a high speed during the first period and performed at a low speed during the second period.
    Type: Application
    Filed: November 1, 2021
    Publication date: May 5, 2022
    Inventors: Kohichi Nakamura, Hiroaki Kameyama, Koichiro Iwata, Yu Arishima
  • Publication number: 20220140838
    Abstract: A ramp signal output circuit includes a first reference current source transistor to which a current is supplied from a current source, a first line connecting a gate of the first reference current source transistor and a gate of a first current source transistor, a branch point where a second line branches from the first line, a first ramp signal generation unit connected to the first current source transistor, and a second ramp signal generation unit connected to a second current source transistor, wherein the second line is connected to a gate of the second current source transistor.
    Type: Application
    Filed: October 26, 2021
    Publication date: May 5, 2022
    Inventors: Seiichirou Sakai, Kazuo Yamazaki, Hiroaki Kameyama
  • Patent number: 11134018
    Abstract: A communication device that is used in a multi-point communication includes: a receiver, a processor and a transmitter. The receiver receives, from a target communication device included among one or more destination communication devices of the communication device, information that indicates a reception bandwidth allocated to a data transmission conducted from the communication device to the target communication device. The processor calculates a transmission bandwidth to be allocated to the data transmission conducted from the communication device to the target communication device according to information relating to the one or more destination communication devices. The transmitter transmits data to the target communication device at a rate that does not exceed an upper limit transmission rate. The upper limit transmission rate is determined according to a smaller one of values of the reception bandwidth and the transmission bandwidth.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: September 28, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Hiroaki Kameyama, Shinichi Sazawa
  • Patent number: 11115608
    Abstract: According to the present disclosure, column circuits operate selectively in a first drive mode to output a comparison signal or a second drive mode to acquire a correction value of a first reference signal and a second reference signal, and a selector circuit of a second column circuit selects the same reference signal out of the first reference signal and the second reference signal in the first drive mode and the second drive mode.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: September 7, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Seiichirou Sakai, Hiroaki Kameyama, Kazuo Yamazaki, Koichiro Iwata, Kohichi Nakamura
  • Patent number: 11095565
    Abstract: A communication device that is used in a multi-point communication includes: a receiver, a processor and a transmitter. The receiver receives, from a target communication device included among one or more destination communication devices of the communication device, information that indicates a reception bandwidth allocated to a data transmission conducted from the communication device to the target communication device. The processor calculates a transmission bandwidth to be allocated to the data transmission conducted from the communication device to the target communication device according to information relating to the one or more destination communication devices. The transmitter transmits data to the target communication device at a rate that does not exceed an upper limit transmission rate. The upper limit transmission rate is determined according to a smaller one of values of the reception bandwidth and the transmission bandwidth.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: August 17, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Hiroaki Kameyama, Shinichi Sazawa
  • Publication number: 20200389638
    Abstract: A photoelectric conversion apparatus includes a control unit configured to change a voltage of an input node from a first voltage toward a predetermined voltage during a predetermined time period after the voltage of the input node changes to the first voltage and before the voltage of the input node changes to a second voltage. A method of driving the photoelectric conversion apparatus includes controlling changing of the voltage of the input node from the first voltage toward the predetermined voltage during the predetermined time period.
    Type: Application
    Filed: June 3, 2020
    Publication date: December 10, 2020
    Inventors: Hiroaki Kameyama, Seiichirou Sakai, Kazuo Yamazaki
  • Patent number: 10841218
    Abstract: A communication relay device receives a packet transmitted from a first communication device to a second communication device and forwards the packet to a correspondent communication relay device. The communication relay device includes: a processor and a communication processor. The processor extracts, from a request packet that requests a connection to the second communication device, a first identifier for indicating the first communication device, when the communication relay device receives the request packet from the first communication device, and generates configuration information including the first identifier.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 17, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Hiroaki Kameyama, Shinichi Sazawa, Tomoyuki Furutono
  • Publication number: 20200314360
    Abstract: According to the present disclosure, column circuits operate selectively in a first drive mode to output a comparison signal or a second drive mode to acquire a correction value of a first reference signal and a second reference signal, and a selector circuit of a second column circuit selects the same reference signal out of the first reference signal and the second reference signal in the first drive mode and the second drive mode.
    Type: Application
    Filed: March 23, 2020
    Publication date: October 1, 2020
    Inventors: Seiichirou Sakai, Hiroaki Kameyama, Kazuo Yamazaki, Koichiro Iwata, Kohichi Nakamura
  • Patent number: 10728356
    Abstract: A communication device includes a memory and a processor. The processor is configured to extract first division data from transmission data when transmitting the transmission data. The processor is configured to store, as held data, the first division data in the memory in association with first identification information that identifies the transmission data. The processor is configured to transmit, to a communication destination, a first transmission packet including the transmission data and information that identifies the held data to cause the communication destination to store second division data which is not included in the held data, among the transmission data in association with the first identification information.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: July 28, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Hiroaki Kameyama, Shinichi Sazawa, Masayoshi Hashima
  • Patent number: 10701188
    Abstract: A device includes a transmission/reception unit configured to receive a packet transmitted from a communication device to a destination device, a control unit configured to separate data received through the packet into transmission data and control information, a replacement process unit configured to generate replacement data resulting from replacing data associated with an identifier with the identifier in the transmission data when data that has been transmitted toward the destination device in association with the identifier is included, and a transmission unit configured to transfer the replacement data toward the destination device, wherein the control unit generates connected data resulting from connecting respective pieces of data obtained by removing the control information from the data, and discards the control information, and the replacement process unit generates the replacement data by replacing data associated with the identifier with the identifier in the connected data.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: June 30, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Hiroaki Kameyama, Shinichi Sazawa
  • Patent number: 10637955
    Abstract: A relay device includes a first relay device connected to a server and a second relay device connected to a client. The first relay device includes a request unit that requests the server to prefetch data in response to a request from the client; a control unit that caches the data in a first cache; and a notification unit that requests the server to prefetch data in response to a current request from the client, and notifies the second relay device of a predetermined signal when the data matches the data cached in the first cache. The second cache of the second relay device caches a part of the data cached in the first cache. The response unit performs, detecting the predetermined signal, a proxy response to the client with the data cached in the second cache in response to a data request from the client.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: April 28, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Hiroaki Kameyama, Shinichi Sazawa