Patents by Inventor Hiroaki Kawano

Hiroaki Kawano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070083938
    Abstract: For monitoring invalid data that causes a computer to execute an invalid operation, an invalidity-monitoring program monitors input/output data sent to and received from a network and an externally connected device, and allows a user to set a variety of invalidity determination and apply an efficient rule. A data-acquisition unit acquires input/output data, which is flowing on a network or an externally connected bus, and the ID of an operator. An invalid-operation-determination unit determines whether an operation is invalid by acquiring attribute information on a user corresponding to the ID from a user-storage unit by referencing a rule corresponding to attribute information from rules stored in an invalidity-rule-storage unit and defined for the respective user, and additionally, by referencing a rule that generally determines an operation as invalid regardless of the attributes stored in the invalidity-rule storage unit.
    Type: Application
    Filed: July 9, 2004
    Publication date: April 12, 2007
    Inventors: Osamu Aoki, Masaharu Shirasugi, Kenichi Koide, Hiroaki Kawano
  • Patent number: 6621233
    Abstract: A power circuit for driving a liquid crystal display panel whereby an afterglow can be prevented from coming out on the liquid crystal display panel when the liquid crystal display panel is turned off. A power down short circuit 10 arranged in a driving power circuit 1 is characterized in that it includes a plurality of power source lines VL1˜VL5 provided corresponding to a plurality of voltage level V1˜V5 and also include a plurality of N-channel MOS transistors M6˜M9 short-circuiting adjacent power source lines each other when detecting if the liquid crystal display line has been turned off. The afterglow is prevented from coming out on the liquid crystal display panel by preventing the lights-on of the liquid crystal element that is caused by a slow fall time of the electric potential of the power source line.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: September 16, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hiroaki Kawano
  • Publication number: 20020195965
    Abstract: A power circuit for driving a liquid crystal display panel whereby an afterglow can be prevented from coming out on the liquid crystal display panel when the liquid crystal display panel is turned off. A power down short circuit 10 arranged in a driving power circuit 1 is characterized in that it includes a plurality of power source lines VL1˜VL5 provided corresponding to a plurality of voltage level V1˜V5 and also include a plurality of N-channel MOS transistors M6˜M9 short-circuiting adjacent power source lines each other when detecting if the liquid crystal display line has been turned off. The afterglow is prevented from coming out on the liquid crystal display panel by preventing the lights-on of the liquid crystal element that is caused by a slow fall time of the electric potential of the power source line.
    Type: Application
    Filed: May 31, 2002
    Publication date: December 26, 2002
    Inventor: Hiroaki Kawano
  • Patent number: 6218877
    Abstract: A semiconductor device capable of easily adjusting an internal delay time is provided with a phase adjusting circuit, wherein the phase adjusting circuit comprises an internal delay reproduction circuit that reproduces the sum of a delay time required for an input signal to be input to the phase adjusting circuit and a delay time required for an output signal to be output from the phase adjusting circuit. A delay adjusting circuit connected with the internal delay reproduction circuit upstream or downstream relative thereto, generates a given delay time for adjusting the internal delay time reproduced by the internal delay reproduction circuit. A delay time control section is connected with the delay adjusting circuit and controls the delay time generated by the delay adjusting circuit. A phase comparator compares a phase of a signal passed through the delay time adjusting circuit with a signal inputted to the phase adjusting circuit.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: April 17, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Kazuhiko Oyama, Hiroaki Kawano
  • Patent number: 5239656
    Abstract: A self-error-correcting semiconductor memory device having a programmable ROM for storing first and second data, at least one temporary register for temporarily storing data and a one-time PROM for writing one time, wherein first data stored in a true address and second data identical to the first data stored in a dummy address both within the programmable ROM are outputted to a data bus and multiplied with each other so as to obtain a third data for performing an error correction.
    Type: Grant
    Filed: April 17, 1990
    Date of Patent: August 24, 1993
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hiroaki Kawano