Patents by Inventor Hiroaki Matsubara
Hiroaki Matsubara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170148766Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.Type: ApplicationFiled: February 2, 2017Publication date: May 25, 2017Applicant: J-DEVICES CORPORATIONInventors: Takeshi MIYAKOSHI, Sumikazu HOSOYAMADA, Yoshikazu KUMAGAYA, Tomoshige CHIKAI, Shingo NAKAMURA, Hiroaki MATSUBARA, Shotaro SAKUMOTO
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Publication number: 20170116978Abstract: A voice synthesizing apparatus includes: a voice inputter (102) configured to input a voice; an obtainer (22) configured to obtain a primary response to the voice inputted by the voice inputter (102); an analyzer (112) configured to analyze whether the primary response includes a repetition target; and a voice synthesizer (24) configured to, in a case where the analyzed primary response is determined to include the repetition target, synthesize a voice from a secondary response that includes the repetition target repeated at least twice to output the voice.Type: ApplicationFiled: July 2, 2015Publication date: April 27, 2017Inventor: Hiroaki MATSUBARA
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Patent number: 9635762Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.Type: GrantFiled: July 20, 2015Date of Patent: April 25, 2017Assignee: J-DEVICES CORPORATIONInventors: Shinji Watanabe, Sumikazu Hosoyamada, Shingo Nakamura, Hiroshi Demachi, Takeshi Miyakoshi, Tomoshige Chikai, Kiminori Ishido, Hiroaki Matsubara, Takashi Nakamura, Hirokazu Honda, Yoshikazu Kumagaya, Shotaro Sakumoto, Toshihiro Iwasaki, Michiaki Tamakawa
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Publication number: 20170110111Abstract: The present invention is provided with: a voice input section that receives a remark (a question) via a voice signal; a reply creation section that creates a voice sequence of a reply (response) to the remark; a pitch analysis section that analyzes the pitch of a first segment (e.g., word ending) of the remark; and a voice generation section (a voice synthesis section, etc.) that generates a reply, in the form of voice, represented by the voice sequence. The voice generation section controls the pitch of the entire reply in such a manner that the pitch of a second segment (e.g., word ending) of the reply assumes a predetermined pitch (e.g., five degrees down) with respect to the pitch of the first segment of the remark. Such arrangements can realize synthesis of replying voice capable of giving a natural feel to the user.Type: ApplicationFiled: December 12, 2016Publication date: April 20, 2017Inventors: Hiroaki MATSUBARA, Junya URA, Takehiko KAWAHARA, Yuji HISAMINATO, Katsuji YOSHIMURA
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Patent number: 9601450Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.Type: GrantFiled: March 26, 2015Date of Patent: March 21, 2017Assignee: J-DEVICES CORPORATIONInventors: Takeshi Miyakoshi, Sumikazu Hosoyamada, Yoshikazu Kumagaya, Tomoshige Chikai, Shingo Nakamura, Hiroaki Matsubara, Shotaro Sakumoto
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Patent number: 9586720Abstract: A pallet includes columns, an upper deck, and a lower deck. The upper deck links upper ends of the columns such that upper surfaces of the columns and upper deck form an upper deck surface. The lower deck links lower ends of the columns such that lower surfaces of the columns and lower deck form a lower deck surface. Fork insertion structures receive forks of a lift apparatus inserted thereto from four sides of the pallet. Outer circumferential projections are formed along a peripheral edge of the upper deck surface, including an extended portion extending outward from the peripheral edge, and a support portion protruding upward from the extended portion. The support portion has a first height in an insertion-corresponding region, and a second height in a general region, the first height being equal to a thickness of the lower deck, the second height being greater than the first height.Type: GrantFiled: June 1, 2016Date of Patent: March 7, 2017Assignee: Sanko Co., Ltd.Inventor: Hiroaki Matsubara
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Patent number: 9553052Abstract: A magnetic shielding package of a non-volatile magnetic memory element, including: a soft magnetic material support plate 12; a first insulating material layer 13 formed on the support plate; a non-volatile magnetic memory element 11 fixed on the first insulating material layer; a second insulating material layer 14 that encapsulates the memory element and the periphery thereof; in the second insulating material layer, a wiring layer 15, a soft magnetic layer 15b or 25 and a conductive portion 16 connecting an electrode of the circuit surface of the memory element and the wiring layer; and a magnetic shield part 17 containing a soft magnetic material arranged like a wall at a distance from a side surface of the memory element so as to surround the memory element side surface partially or entirely, the magnetic shield part being magnetically connected to the soft magnetic layer.Type: GrantFiled: December 9, 2015Date of Patent: January 24, 2017Assignee: J-DEVICES CORPORATIONInventors: Hiroaki Matsubara, Toshihiro Iwasaki, Tomoshige Chikai, Kiminori Ishido, Shinji Watanabe, Michiaki Tamakawa
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Patent number: 9520374Abstract: The semiconductor device can prevent damages on a semiconductor chip even when a soldering material is used for bonding the back surface of the semiconductor chip to the junction plane of a chip junction portion such as an island or a die pad. This semiconductor device includes a semiconductor chip and a chip junction portion having a junction plane that is bonded to the back surface of the semiconductor chip with a soldering material. The junction plane is smaller in size than the back surface of the semiconductor chip. This semiconductor device may further include a plurality of extending portions which extend respectively from the periphery of the junction plane to directions parallel with the junction plane.Type: GrantFiled: July 2, 2014Date of Patent: December 13, 2016Assignee: ROHM CO., LTD.Inventors: Yasumasa Kasuya, Motoharu Haga, Hiroaki Matsubara
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Publication number: 20160307854Abstract: A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first terminals spaced in a first direction, second terminals spaced in the first direction and opposite to the first terminals in a second direction perpendicular to the first direction, and a support terminal connected to the die pad. The sealing resin encapsulates portions of the first and second terminals, a portion of the support terminal, the semiconductor element circuit and the die pad. The sealing resin has two first side surfaces spaced apart in the second direction and two second side surfaces spaced apart in the first direction. The first terminals and second terminals are exposed from the first side surfaces, while none of the elements of the conductive support is exposed from the second side surfaces.Type: ApplicationFiled: April 11, 2016Publication date: October 20, 2016Inventors: Hiroaki MATSUBARA, Yasumasa KASUYA
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Publication number: 20160272365Abstract: A pallet includes columns, an upper deck, and a lower deck. The upper deck links upper ends of the columns such that upper surfaces of the columns and upper deck form an upper deck surface. The lower deck links lower ends of the columns such that lower surfaces of the columns and lower deck form a lower deck surface. Fork insertion structures receive forks of a lift apparatus inserted thereto from four sides of the pallet. Outer circumferential projections are formed along a peripheral edge of the upper deck surface, including an extended portion extending outward from the peripheral edge, and a support portion protruding upward from the extended portion. The support portion has a first height in an insertion-corresponding region, and a second height in a general region, the first height being equal to a thickness of the lower deck, the second height being greater than the first height.Type: ApplicationFiled: June 1, 2016Publication date: September 22, 2016Inventor: Hiroaki MATSUBARA
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Publication number: 20160228472Abstract: An object of the present invention is to provide a stem cell applicable to regenerative therapeutic method, and to provide a technique to carry out regenerative therapy using the cell. A collected cardiac tissue fragment is enzymatically treated to prepare a cell suspension. Then using the cell suspension, following steps are carried out: (1) separation of cells by the density gradient method, (2) suspension-culture in a culture medium containing fibroblast growth factor and epidermal growth factor and (3) selection and separation of cells forming a floating sphere to obtain pluripotent stem cells. Thus-obtained pluripotent stem cells are used to carry out regenerative therapy.Type: ApplicationFiled: October 29, 2015Publication date: August 11, 2016Inventors: Hidemasa Oh, Kento Tateishi, Hiroaki Matsubara
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Publication number: 20160172580Abstract: A magnetic shielding package of a non-volatile magnetic memory element, including: a soft magnetic material support plate 12; a first insulating material layer 13 formed on the support plate; a non-volatile magnetic memory element 11 fixed on the first insulating material layer; a second insulating material layer 14 that encapsulates the memory element and the periphery thereof; in the second insulating material layer, a wiring layer 15, a soft magnetic layer 15b or 25 and a conductive portion 16 connecting an electrode of the circuit surface of the memory element and the wiring layer; and a magnetic shield part 17 containing a soft magnetic material arranged like a wall with a distance from a side surface of the memory element so as to surround the memory element side surface partially or entirely, the magnetic shield part being magnetically connected to the soft magnetic layer.Type: ApplicationFiled: December 9, 2015Publication date: June 16, 2016Inventors: Hiroaki MATSUBARA, Toshihiro IWASAKI, Tomoshige CHIKAI, Kiminori ISHIDO, Shinji WATANABE, Michiaki TAMAKAWA
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Patent number: 9368474Abstract: A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thicknType: GrantFiled: September 10, 2015Date of Patent: June 14, 2016Assignee: J-DEVICES CORPORATIONInventors: Hiroaki Matsubara, Tomoshige Chikai, Kiminori Ishido, Takashi Nakamura, Hirokazu Honda, Hiroshi Demachi, Yoshikazu Kumagaya, Shotaro Sakumoto, Shinji Watanabe, Sumikazu Hosoyamada, Shingo Nakamura, Takeshi Miyakoshi, Toshihiro Iwasaki, Michiaki Tamakawa
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Patent number: 9362200Abstract: A semiconductor package includes a support substrate arranged with a first aperture reaching a semiconductor device on a rear side, the semiconductor device is bonded via an adhesive to a surface of the support substrate, an insulating layer covering the semiconductor device, and wiring for connecting the semiconductor device and an external terminal through the insulating layer. The adhesive may form a part of the first aperture. In addition, a heat dissipation part may be arranged in the first aperture and a metal material may be filled in the first aperture.Type: GrantFiled: June 19, 2015Date of Patent: June 7, 2016Assignee: J-DEVICES CORPORATIONInventors: Hirokazu Honda, Shinji Watanabe, Toshihiro Iwasaki, Kiminori Ishido, Koichiro Niwa, Takeshi Miyakoshi, Sumikazu Hosoyamada, Yoshikazu Kumagaya, Tomoshige Chikai, Shingo Nakamura, Shotaro Sakumoto, Hiroaki Matsubara
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Patent number: 9301917Abstract: Provided is a pharmaceutical composition, including a drug and a collagen, in which the composition is satisfactory in handleability and has sustained-release property. The sustained-release pharmaceutical composition includes: a drug; a collagen; and at least one kind of sugar selected from monosaccharides, disaccharides, trisaccharides, and tetrasaccharides. The inventors of the present invention have found that the in vivo administration of a collagen solution containing a sugar results in the gelation of a collagen. Based on this finding, the inventors have found that a composition containing a drug, a collagen, and a sugar can control the release rate of the drug, and such composition can be used as a sustained-release pharmaceutical composition.Type: GrantFiled: October 14, 2011Date of Patent: April 5, 2016Assignees: Kyoto University, Kyoto Prefectural Public University Corporation, Kaken Pharmaceutical Co., Ltd., Koken Co., Ltd.Inventors: Masanori Fukushima, Hiroaki Matsubara, Satoaki Matoba, Shigeki Hijikata, Yu Aso, Tsutomu Sato
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Publication number: 20160086597Abstract: The present invention is provided with: a voice input section that receives a remark (a question) via a voice signal; a reply creation section that creates a voice sequence of a reply (response) to the remark; a pitch analysis section that analyzes the pitch of a first segment (e.g., word ending) of the remark; and a voice generation section (a voice synthesis section, etc.) that generates a reply, in the form of voice, represented by the voice sequence. The voice generation section controls the pitch of the entire reply in such a manner that the pitch of a second segment (e.g., word ending) of the reply assumes a predetermined pitch (e.g., five degrees down) with respect to the pitch of the first segment of the remark. Such arrangements can realize synthesis of replying voice capable of giving a natural feel to the user.Type: ApplicationFiled: June 2, 2014Publication date: March 24, 2016Inventors: Hiroaki MATSUBARA, Junya URA, Takehiko KAWAHARA, Yuji HISAMINATO, Katsuji YOSHIMURA
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Publication number: 20160079204Abstract: A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thicknType: ApplicationFiled: September 10, 2015Publication date: March 17, 2016Inventors: Hiroaki Matsubara, Tomoshige Chikai, Kiminori Ishido, Takashi Nakamura, Hirokazu Honda, Hiroshi Demachi, Yoshikazu Kumagaya, Shotaro Sakumoto, Shinji Watanabe, Sumikazu Hosoyamada, Shingo Nakamura, Takeshi Miyakoshi, Toshihiro Iwasaki, Michiaki Tamakawa
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Publication number: 20160027715Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.Type: ApplicationFiled: July 20, 2015Publication date: January 28, 2016Inventors: Shinji WATANABE, Sumikazu HOSOYAMADA, Shingo NAKAMURA, Hiroshi DEMACHI, Takeshi MIYAKOSHI, Tomoshige CHIKAI, Kiminori ISHIDO, Hiroaki MATSUBARA, Takashi NAKAMURA, Hirokazu HONDA, Yoshikazu KUMAGAYA, Shotaro SAKUMOTO, Toshihiro IWASAKI, Michiaki TAMAKAWA
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Publication number: 20160027695Abstract: The invention provides a semiconductor device low in height and having low heat resistance, and a method of manufacturing the semiconductor device.Type: ApplicationFiled: July 16, 2015Publication date: January 28, 2016Inventors: Yoshihiko IKEMOTO, Hiroshi INOUE, Kiminori ISHIDO, Hiroaki MATSUBARA, Yukari IMAIZUMI
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Publication number: 20160007464Abstract: An electronic device includes an electronic element, a plurality of first sub-electrodes arrayed in a first direction, a plurality of second sub-electrodes arrayed in a second direction that is orthogonal to the first direction, a dummy electrode, and a sealing resin. The sealing resin has a resin back surface from which the plurality of first sub-electrodes, the plurality of second sub-electrodes and the dummy electrode are exposed. The plurality of second sub-electrodes are located further in the first direction than any of the plurality of first sub-electrodes. The plurality of first sub-electrodes are located further in the second direction than any of the plurality of second sub-electrodes. The dummy electrode is located further in the first direction than any of the plurality of first sub-electrodes, and is located further in the second direction than any of the plurality of second sub-electrodes.Type: ApplicationFiled: July 1, 2015Publication date: January 7, 2016Inventors: Hiroaki MATSUBARA, Yasumasa KASUYA, Taro NISHIOKA