Patents by Inventor Hiroaki Naruse
Hiroaki Naruse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11751417Abstract: A device comprising a first layer, a sealing layer and a resin layer stacked in that order and an organic layer arranged between the first layer and the sealing layer in a pixel region is provided. The first, sealing and resin layers have openings for exposing an electrode in a peripheral region. The sealing layer includes second and third layers each having a water permeability lower than the first layer, and a fourth layer arranged between the second layer and the third layer and having a defect density lower than the second layer. A step of the second layer arranged above the end of the opening of the first layer is covered with the fourth layer and a step of the third layer arranged above the end of the opening of the first layer is covered with the resin layer.Type: GrantFiled: April 23, 2021Date of Patent: September 5, 2023Assignee: CANON KABUSHIKI KAISHAInventors: Yojiro Matsuda, Masaki Kurihara, Daisuke Shimoyama, Hiroaki Naruse
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Publication number: 20220255042Abstract: An organic device includes a reflective film arranged on a substrate, a plurality of lower electrodes arranged above the reflective film, an organic function film configured to cover the plurality of lower electrodes, and an upper electrode arranged on the organic function film. A potential difference between the upper electrode and the reflective film is lower than a threshold voltage at which the organic function film operates.Type: ApplicationFiled: April 27, 2022Publication date: August 11, 2022Inventors: Hiroaki Naruse, Koji Ishizuya, Yojiro Matsuda, Takayuki Ito, Hiroaki Sano
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Publication number: 20210265591Abstract: A device comprising a first layer, a sealing layer and a resin layer stacked in that order and an organic layer arranged between the first layer and the sealing layer in a pixel region is provided. The first, sealing and resin layers have openings for exposing an electrode in a peripheral region. The sealing layer includes second and third layers each having a water permeability lower than the first layer, and a fourth layer arranged between the second layer and the third layer and having a defect density lower than the second layer. A step of the second layer arranged above the end of the opening of the first layer is covered with the fourth layer and a step of the third layer arranged above the end of the opening of the first layer is covered with the resin layer.Type: ApplicationFiled: April 23, 2021Publication date: August 26, 2021Inventors: Yojiro Matsuda, Masaki Kurihara, Daisuke Shimoyama, Hiroaki Naruse
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Patent number: 11018316Abstract: A device comprising a first layer, a sealing layer and a resin layer stacked in that order and an organic layer arranged between the first layer and the sealing layer in a pixel region is provided. The first, sealing and resin layers have openings for exposing an electrode in a peripheral region. The sealing layer includes second and third layers each having a water permeability lower than the first layer, and a fourth layer arranged between the second layer and the third layer and having a defect density lower than the second layer. A step of the second layer arranged above the end of the opening of the first layer is covered with the fourth layer and a step of the third layer arranged above the end of the opening of the first layer is covered with the resin layer.Type: GrantFiled: March 27, 2019Date of Patent: May 25, 2021Assignee: CANON KABUSHIKI KAISHAInventors: Yojiro Matsuda, Masaki Kurihara, Daisuke Shimoyama, Hiroaki Naruse
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Patent number: 10543685Abstract: A semiconductor device used for a liquid discharge head is provided. The device includes a wiring layer, an insulating member formed above the wiring layer, a heat generation element arranged above and in contact with the insulating member, and electrically connected to the wiring layer, a metal member arranged above and in contact with the insulating member, and electrically connected to the wiring layer, and an electrically conductive member covering an upper surface of the metal member and electrically connected to the wiring layer through the metal member. A resistivity of the electrically conductive member is less than a resistivity of the metal member and a resistivity of the heat generation element. The heat generation element and the metal member are separated from each other.Type: GrantFiled: June 22, 2018Date of Patent: January 28, 2020Assignee: CANON KABUSHIKI KAISHAInventors: Hiroaki Naruse, Akihiro Shimizu, Toru Eto
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Publication number: 20190334115Abstract: A device comprising a first layer, a sealing layer and a resin layer stacked in that order and an organic layer arranged between the first layer and the sealing layer in a pixel region is provided. The first, sealing and resin layers have openings for exposing an electrode in a peripheral region. The sealing layer includes second and third layers each having a water permeability lower than the first layer, and a fourth layer arranged between the second layer and the third layer and having a defect density lower than the second layer. A step of the second layer arranged above the end of the opening of the first layer is covered with the fourth layer and a step of the third layer arranged above the end of the opening of the first layer is covered with the resin layer.Type: ApplicationFiled: March 27, 2019Publication date: October 31, 2019Inventors: Yojiro Matsuda, Masaki Kurihara, Daisuke Shimoyama, Hiroaki Naruse
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Patent number: 10312283Abstract: An imaging device includes a pixel circuit region that includes a plurality of pixel circuits arranged in an array therein and a plurality of light guide portions. The imaging device also includes a peripheral circuit region that is positioned at a periphery of the pixel circuit region and includes a peripheral circuit. The imaging device also includes an intermediate region that is positioned between the pixel circuit region and the peripheral circuit region, forms a boundary with the pixel circuit region and the peripheral circuit region, and includes a plurality of dummy light guide portions and a plurality of contacts through which a reference potential of the plurality of pixel circuits is supplied.Type: GrantFiled: July 3, 2018Date of Patent: June 4, 2019Assignee: CANON KABUSHIKI KAISHAInventors: Aiko Kato, Shingo Kitamura, Takehiro Toyoda, Hiroaki Naruse
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Publication number: 20190001678Abstract: A semiconductor device used for a liquid discharge head is provided. The device includes a wiring layer, an insulating member formed above the wiring layer, a heat generation element arranged above and in contact with the insulating member, and electrically connected to the wiring layer, a metal member arranged above and in contact with the insulating member, and electrically connected to the wiring layer, and an electrically conductive member covering an upper surface of the metal member and electrically connected to the wiring layer through the metal member. A resistivity of the electrically conductive member is less than a resistivity of the metal member and a resistivity of the heat generation element. The heat generation element and the metal member are separated from each other.Type: ApplicationFiled: June 22, 2018Publication date: January 3, 2019Inventors: Hiroaki Naruse, Akihiro Shimizu, Toru Eto
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Publication number: 20180331145Abstract: An imaging device includes a pixel circuit region that includes a plurality of pixel circuits arranged in an array therein and a plurality of light guide portions. The imaging device also includes a peripheral circuit region that is positioned at a periphery of the pixel circuit region and includes a peripheral circuit. The imaging device also includes an intermediate region that is positioned between the pixel circuit region and the peripheral circuit region, forms a boundary with the pixel circuit region and the peripheral circuit region, and includes a plurality of dummy light guide portions and a plurality of contacts through which a reference potential of the plurality of pixel circuits is supplied.Type: ApplicationFiled: July 3, 2018Publication date: November 15, 2018Inventors: Aiko Kato, Shingo Kitamura, Takehiro Toyoda, Hiroaki Naruse
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Patent number: 10043842Abstract: An imaging device includes a pixel circuit region that includes a plurality of pixel circuits arranged in an array therein and a plurality of light guide portions. The imaging device also includes a peripheral circuit region that is positioned at a periphery of the pixel circuit region and includes a peripheral circuit. The imaging device also includes an intermediate region that is positioned between the pixel circuit region and the peripheral circuit region, forms a boundary with the pixel circuit region and the peripheral circuit region, and includes a plurality of dummy light guide portions and a plurality of contacts through which a reference potential of the plurality of pixel circuits is supplied.Type: GrantFiled: October 3, 2014Date of Patent: August 7, 2018Assignee: CANON KABUSHIKI KAISHAInventors: Aiko Kato, Shingo Kitamura, Takehiro Toyoda, Hiroaki Naruse
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Patent number: 9825077Abstract: A photoelectric conversion device includes a photoelectric conversion region having a plurality of photoelectric conversion elements and a first MOS transistor configured to read a signal in response to an electric charge of each photoelectric conversion element; and a peripheral circuit region having a second MOS transistor configured to drive the first MOS transistor and/or amplify the signal read from the photoelectric conversion region, the photoelectric conversion region and the peripheral circuit region being located on the same semiconductor substrate, wherein an impurity concentration in a drain of the first MOS transistor is lower than an impurity concentration in a drain of the second MOS transistor.Type: GrantFiled: July 22, 2015Date of Patent: November 21, 2017Assignee: Canon Kabushiki KaishaInventors: Takanori Watanabe, Tetsuya Itano, Hidekazu Takahashi, Shunsuke Takimoto, Kotaro Abukawa, Hiroaki Naruse, Shigeru Nishimura, Masatsugu Itahashi
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Patent number: 9559136Abstract: A semiconductor device manufacturing method includes a step of forming a hole reaching a first insulating layer over a first conductive member; a step of forming a trench reaching a second insulating layer and in communication with the hole; a step of forming an opening exposing the first conductive member in the hole; and a step of forming a second conductive member connected to the first conductive member by embedding a conductive material in the opening, the hole, and the trench. The trench is formed under an etching condition such that the etching rate with respect to the second insulating layer is lower than the etching rate with respect to the third insulating layer.Type: GrantFiled: February 10, 2015Date of Patent: January 31, 2017Assignee: Canon Kabushiki KaishaInventors: Aiko Kato, Yu Nishimura, Hiroaki Naruse, Keita Torii
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Patent number: 9437651Abstract: One portion of a first insulator film, which is positioned on a second semiconductor region, and another portion of the first insulator film, which is positioned on a third semiconductor region, are removed, while a first portion of the first insulator film, which is positioned on a first semiconductor region is remained, one portion of a second insulator film, which is positioned on the first semiconductor region, and another portion of the second insulator film, which is positioned on the second semiconductor region, are removed, while a second portion of the second insulator film, which is positioned on the third semiconductor region is remained, and a metal film that covers the first portion, the second semiconductor region, and the second portion, and the second semiconductor region are caused to react with each other and a metal compound layer is formed.Type: GrantFiled: December 2, 2014Date of Patent: September 6, 2016Assignee: Canon Kabushiki KaishaInventors: Hiroaki Naruse, Tomoyuki Tamura, Atsushi Ogino
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Patent number: 9391227Abstract: A substrate includes a first region having photoelectric conversion portions and a second region having an element included in a signal processing circuit. An insulator including first and second parts respectively arranged on the first and second regions is formed on the substrate. Openings are formed in the insulator and respectively superposed on the photoelectric conversion portions. A first member is formed in the openings and on the second part of the insulator after forming the openings. At least a portion of the first member arranged on the second region is removed. The first member is planarized after removing at least the portion of the first member. A second insulator is formed on the first and second regions after planarizing the first member. A through-hole is formed in a part of the second insulator. No planarization with grinding is performed after forming the second insulator and before forming the through-hole.Type: GrantFiled: August 5, 2013Date of Patent: July 12, 2016Assignee: Canon Kabushiki KaishaInventors: Tadashi Sawayama, Takashi Usui, Akihiro Kawano, Hiroaki Naruse, Sho Suzuki, Takehito Okabe, Masatsugu Itahashi, Daisuke Uki
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Patent number: 9331121Abstract: A method of manufacturing a photoelectric conversion apparatus which includes a pixel circuit section having a well where a photoelectric conversion element and an amplification element configured to generate a signal based on an amount of charge generated in the photoelectric conversion element are arranged, and a peripheral circuit section having a MOS transistor. The method includes forming a dielectric film for covering the photoelectric conversion element, the amplification element, and a gate electrode of the MOS transistor and forming, by etching the dielectric film, a side spacer by remaining a portion of the dielectric film on a side surface of the gate electrode while protecting by a resist, wherein an opening is formed in the dielectric film of the pixel circuit section with the etching, and a contact for defining a potential of the well is formed through the opening.Type: GrantFiled: November 4, 2014Date of Patent: May 3, 2016Assignee: CANON KABUSHIKI KAISHAInventors: Yusuke Onuki, Hiroaki Naruse, Masashi Kusukawa, Katsunori Hirota
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Patent number: 9293486Abstract: An image capturing device includes an intermediate region located between a pixel circuit region and a peripheral circuit region and forming a boundary with the pixel circuit region and the peripheral circuit region. The pixel circuit region, the peripheral circuit region, and the intermediate region are provided with a semiconductor layer, a first wiring layer on the semiconductor layer, and a second wiring layer located away from the semiconductor layer relative to the first wiring layer. Pixel circuits and a peripheral circuit are connected via one of at least the first wiring layer and the second wiring layer in the intermediate region. The area occupancy of the one wiring layer in the intermediate region relative to a total area thereof is between 0.5 times and 1.5 times the area occupancy of the one wiring layer in the pixel circuit region relative to a total area thereof.Type: GrantFiled: October 6, 2014Date of Patent: March 22, 2016Assignee: CANON KABUSHIKI KAISHAInventors: Aiko Kato, Shingo Kitamura, Takehiro Toyoda, Hiroaki Naruse
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Patent number: 9247173Abstract: Each of a plurality of pixel circuits is an insulated gate transistor and includes a first kind transistor having a maximum value of a gate potential difference to be applied equal to or higher than a first value. Each of a plurality of analog signal processing circuits is an insulated gate transistor and includes a second kind transistor having a maximum value of a gate potential difference to be applied equal to or lower than a second value that is lower than the first value. Each of a plurality of analog signal processing circuits does not include an insulated gate transistor having a maximum value of a gate potential difference to be applied not higher than the second value.Type: GrantFiled: December 22, 2014Date of Patent: January 26, 2016Assignee: CANON KABUSHIKI KAISHAInventors: Kazuo Kokumai, Yusuke Onuki, Hiroaki Naruse, Masashi Kusukawa, Katsunori Hirota, Nobuyuki Endo, Kazuo Yamazaki, Hiroaki Kobayashi
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Patent number: 9239423Abstract: An exemplary embodiment according to the present invention is an imaging device including a substrate in which a plurality of light receiving portions is arranged, an insulator configured to be arranged on the substrate, a plurality of first members configured to be arranged on the substrate so that each of projections of the plurality of first members on the substrate overlaps at least in part with any of the plurality of light receiving portions, and each of the plurality of first members sides is surrounded by the insulator, a second member configured to be arranged on the insulator and the plurality of first members, and a light shielding portion configured to be arranged in the second member.Type: GrantFiled: August 2, 2013Date of Patent: January 19, 2016Assignee: Canon Kabushiki KaishaInventor: Hiroaki Naruse
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Publication number: 20150325610Abstract: A photoelectric conversion device includes a photoelectric conversion region having a plurality of photoelectric conversion elements and a first MOS transistor configured to read a signal in response to an electric charge of each photoelectric conversion element; and a peripheral circuit region having a second MOS transistor configured to drive the first MOS transistor and/or amplify the signal read from the photoelectric conversion region, the photoelectric conversion region and the peripheral circuit region being located on the same semiconductor substrate, wherein an impurity concentration in a drain of the first MOS transistor is lower than an impurity concentration in a drain of the second MOS transistor.Type: ApplicationFiled: July 22, 2015Publication date: November 12, 2015Inventors: Takanori Watanabe, Tetsuya Itano, Hidekazu Takahashi, Shunsuke Takimoto, Kotaro Abukawa, Hiroaki Naruse, Shigeru Nishimura, Masatsugu Itahashi
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Patent number: 9171799Abstract: A photoelectric conversion apparatus includes a semiconductor substrate on which a photoelectric conversion element and a transistor are arranged and a plurality of wiring layers including a first wiring layer and a second wiring layer above the first wiring layer, in which a connection between the semiconductor substrate and any of the plurality of wiring layers, between a gate electrode of the transistor and any of the plurality of wiring layers, or between the first wiring layer and the second wiring layer, has a stacked contact structure.Type: GrantFiled: March 24, 2011Date of Patent: October 27, 2015Assignee: CANON KABUSHIKI KAISHAInventors: Hiroaki Naruse, Kenji Togo, Masatsugu Itahashi