Patents by Inventor Hiroaki Niimi

Hiroaki Niimi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TITANIUM SILICIDE FORMATION IN A NARROW SOURCE-DRAIN CONTACT
    Publication number: 20150380304
    Abstract: Aspects of the present invention relate to approaches for forming a narrow source-drain contact in a semiconductor device. A contact trench can be etched to a source-drain region of the semiconductor device. A titanium liner can be deposited in this contact trench such that it covers substantially an entirety of the bottom and walls of the contact trench. An x-metal layer can be deposited over the titanium liner on the bottom of the contact trench. A titanium nitride liner can then be formed on the walls of the contact trench. The x-metal layer prevents the nitriding of the titanium liner on the bottom of the contact trench during the formation of the nitride liner.
    Type: Application
    Filed: June 25, 2014
    Publication date: December 31, 2015
    Inventors: Min Gyu Sung, Kwanyong Lim, Hiroaki Niimi
  • Integrated circuits with metal-titanium oxide contacts and fabrication methods
    Patent number: 9224638
    Abstract: Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: December 29, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hiroaki Niimi, Kisik Choi, Hoon Kim, Andy Wei, Guillaume Bouche
  • Methods to enhance effective work function of mid-gap metal by incorporating oxygen and hydrogen at a low thermal budget
    Patent number: 9202884
    Abstract: A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: December 1, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroaki Niimi, James Joseph Chambers
  • INTEGRATED CIRCUITS WITH METAL-TITANIUM OXIDE CONTACTS AND FABRICATION METHODS
    Publication number: 20150325473
    Abstract: Devices and methods for forming semiconductor devices with metal-titanium oxide contacts are provided. One intermediate semiconductor device includes, for instance: a substrate, at least one field-effect transistor disposed on the substrate, a first contact region positioned over at least a first portion of the at least one field-effect transistor between a spacer and an interlayer dielectric, and a second contact region positioned over at least a second portion of the at least one field-effect transistor between a spacer and an interlayer dielectric. One method includes, for instance: obtaining an intermediate semiconductor device and forming at least one contact on the intermediate semiconductor device.
    Type: Application
    Filed: May 12, 2014
    Publication date: November 12, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Hiroaki NIIMI, Kisik CHOI, Hoon KIM, Andy WEI, Guillaume BOUCHE
  • System and method for mitigating oxide growth in a gate dielectric
    Patent number: 9177806
    Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: November 3, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Malcolm J. Bevan, Haowen Bu, Hiroaki Niimi, Husam N. Alshareef
  • STRUCTURE AND METHOD FOR METAL GATE STACK OXYGEN CONCENTRATION CONTROL USING AN OXYGEN DIFFUSION BARRIER LAYER AND A SACRIFICIAL OXYGEN GETTERING LAYER
    Publication number: 20150311126
    Abstract: A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.
    Type: Application
    Filed: June 15, 2015
    Publication date: October 29, 2015
    Inventors: James Joseph Chambers, Hiroaki Niimi
  • HIGH-K / METAL GATE CMOS TRANSISTORS WITH TiN GATES
    Publication number: 20150287643
    Abstract: An integrated circuit with a thick TiN metal gate with a work function greater than 4.85 eV and with a thin TiN metal gate with a work function less than 4.25 eV. An integrated circuit with a replacement gate PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a replacement gate NMOS TiN metal gate transistor with a workfunction less than 4.25 eV. An integrated circuit with a gate first PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a gate first NMOS TiN metal gate transistor with a workfunction less than 4.25 eV.
    Type: Application
    Filed: May 28, 2015
    Publication date: October 8, 2015
    Inventors: Hiroaki Niimi, Brian K. Kirkpatrick
  • Structure and method for metal gate stack oxygen concentration control using an oxygen diffusion barrier layer and a sacrificial oxygen gettering layer
    Patent number: 9087918
    Abstract: A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: July 21, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Joseph Chambers, Hiroaki Niimi
  • HIGH-K / METAL GATE CMOS TRANSISTORS WITH TiN GATES
    Publication number: 20150187653
    Abstract: An integrated circuit with a thick TiN metal gate with a work function greater than 4.85 eV and with a thin TiN metal gate with a work function less than 4.25 eV. An integrated circuit with a replacement gate PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a replacement gate NMOS TiN metal gate transistor with a workfunction less than 4.25 eV. An integrated circuit with a gate first PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a gate first NMOS TiN metal gate transistor with a workfunction less than 4.25 eV.
    Type: Application
    Filed: December 11, 2014
    Publication date: July 2, 2015
    Inventors: Hiroaki Niimi, Brian K. Kirkpatrick
  • FRINGE CAPACITANCE REDUCTION FOR REPLACEMENT GATE CMOS
    Publication number: 20150187903
    Abstract: A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench
    Type: Application
    Filed: December 22, 2014
    Publication date: July 2, 2015
    Inventors: Hiroaki Niimi, Mahalingam Nandakumar
  • HIGH MOBILITY TRANSISTORS
    Publication number: 20150187773
    Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.
    Type: Application
    Filed: December 17, 2014
    Publication date: July 2, 2015
    Inventors: Hiroaki Niimi, Manoj Mehrotra, Rick L. Wise
  • HYBRID HIGH-K FIRST AND HIGH-K LAST REPLACEMENT GATE PROCESS
    Publication number: 20150187771
    Abstract: An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.
    Type: Application
    Filed: December 22, 2014
    Publication date: July 2, 2015
    Inventors: Hiroaki Niimi, Manoj Mehrotra, Mahalingam Nandakumar
  • HIGH QUALITY DIELECTRIC FOR HI-K LAST REPLACEMENT GATE TRANSISTORS
    Publication number: 20150187659
    Abstract: A replacement metal gate transistor is formed with high quality gate dielectric under the high-k dielectric. The high quality gate dielectric is formed on the substrate at a temperature of at least 850° C. A sacrificial gate dielectric is formed on the high quality gate dielectric and a polysilicon replacement gate is formed on the sacrificial gate dielectric. The polysilicon replacement gate is removed leaving a gate trench. The sacrificial gate dielectric is removed from a bottom of the gate. A high-k dielectric is deposited into the gate trench. Metal gate material is deposited on the high-k dielectric.
    Type: Application
    Filed: December 18, 2014
    Publication date: July 2, 2015
    Inventors: Mahalingam Nandakumar, Hiroaki Niimi
  • HIGH MOBILITY TRANSISTORS
    Publication number: 20150187770
    Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.
    Type: Application
    Filed: December 17, 2014
    Publication date: July 2, 2015
    Inventors: Manoj Mehrotra, Charles Frank Machala, III, Rick L. Wise, Hiroaki Niimi
  • High-k / metal gate CMOS transistors with TiN gates
    Patent number: 9070785
    Abstract: An integrated circuit with a thick TiN metal gate with a work function greater than 4.85 eV and with a thin TiN metal gate with a work function less than 4.25 eV. An integrated circuit with a replacement gate PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a replacement gate NMOS TiN metal gate transistor with a workfunction less than 4.25 eV. An integrated circuit with a gate first PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a gate first NMOS TiN metal gate transistor with a workfunction less than 4.25 eV.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: June 30, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroaki Niimi, Brian K. Kirkpatrick
  • Metal-Gate MOS Transistor and Method of Forming the Transistor with Reduced Gate-to-Source and Gate-to-Drain Overlap Capacitance
    Publication number: 20150179783
    Abstract: The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k gate dielectric along the inside of a sidewall structure which has been formed to lie further away from the source and the drain.
    Type: Application
    Filed: March 2, 2015
    Publication date: June 25, 2015
    Inventors: Manoj Mehrotra, Hiroaki Niimi
  • Transistor performance using a two-step damage anneal
    Patent number: 9054056
    Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: June 9, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroaki Niimi, Jarvis Benjamin Jacobs, Ajith Varghese
  • Transistor performance using a two-step damage anneal
    Patent number: 9029251
    Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: May 12, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Jarvis Benjamin Jacobs, Ajith Varghese
  • Metal-gate MOS transistor and method of forming the transistor with reduced gate-to-source and gate-to-drain overlap capacitance
    Patent number: 9000539
    Abstract: The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k gate dielectric along the inside of a sidewall structure which has been formed to lie further away from the source and the drain.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: April 7, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Manoj Mehrotra, Hiroaki Niimi
  • TRANSISTOR PERFORMANCE USING A TWO-STEP DAMAGE ANNEAL
    Publication number: 20140342521
    Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.
    Type: Application
    Filed: August 5, 2014
    Publication date: November 20, 2014
    Inventors: Hiroaki Niimi, Jarvis Benjamin Jacobs, Ajith Varghese