Abstract: A semiconductor device has an external connection terminal, an internal circuit region, an ESD protection N-MOS transistor provided between the external connection terminal and the internal circuit region to protect an internal element formed in the internal circuit region, and a shallow trench structure provided to isolate the ESD protection N-MOS transistor. A thin insulating film is formed on a drain region of the ESD protection N-MOS transistor. An electrode is disposed above the drain region and on the thin insulating film for receiving a signal from the external connection terminal. The thin insulating film has a film thickness and film properties that allow dielectric breakdown and establish conduction between the electrode and the drain region when a voltage exceeding an absolute maximum rating of the semiconductor device is applied to the electrode.

Abstract: Provided is an electrically erasable and programmable nonvolatile semiconductor memory device having a small hole in a second conductivity-type drain region, a tunnel insulating film formed on the surface of the hole, and a protrusion extended from the floating gate electrode and arranged to fill the hole. Further a tunneling restriction region which is an electrically floating first conductivity type region arranged in a vicinity of the surface of the drain region around the hole to define the size of the tunnel region through which the tunnel current flows.

Abstract: Provided is an electrically erasable and programmable nonvolatile semiconductor memory device having a tunnel region; the tunnel region and the peripheral of the tunnel region are dug down to be made lower, and a depletion electrode, to which an arbitral potential is given to deplete a part of the tunnel region through a depletion electrode insulating film, is arranged in the lowered drain region.

Abstract: In a manufacturing method for an image sensor integrated circuit, a plurality of pixel regions each having a photodiode are arranged on a silicon substrate. A light-transmissive conductive film is formed over the silicon substrate. A protective film is formed on the light-transmissive conductive film while holding a potential of the light-transmissive conductive film at the same potential as that of the silicon substrate.

Abstract: Provided is a semiconductor device in which the first trench isolation regions is placed between a substrate potential-fixing P-type diffusion region of an ESD protection NMOS transistor and source and drain regions of the ESD protection NMOS transistor, and has a depth greater than a depth of the second trench isolation region that is placed between a substrate potential-fixing P-type diffusion region of an NMOS transistor for internal circuit and source and drain regions of the NMOS transistor for internal circuit.

Abstract: Provided is an electrically erasable and programmable nonvolatile semiconductor memory device whose tunnel region formed in the drain region has the second conductivity-type low-impurity-concentration region with the first tunnel insulating film for solely injecting electrons disposed thereon, and the first conductivity-type low-impurity-concentration region with the second tunnel insulating film for solely ejecting electrons disposed thereon, both regions fixed to the same potential as the drain region and having a lower impurity concentration than that of the drain region.

Abstract: Provided is a semiconductor device for performing photoelectric conversion of incident light, including: a p-type substrate (1), an n-type well (2) having a predetermined depth and formed in a predetermined region of the p-type substrate (1), and a depletion layer generated at a junction interface between the p-type substrate (1) and the n-type well (2). In the trenches (22) having a depth larger than that of a depletion layer (K1) generated on a bottom side of the n-type well (2) and a width larger than that of depletion layers (K2, K3) generated on sides of the n-type well (2) are provided so as to remove junction interfaces (J2, J3) on the sides of the n-type well (2), and an insulating layer (21) is buried in the trenches (22).

Abstract: A semiconductor device for performing photoelectric conversion has a semiconductor substrate of a first conductivity type and a well region of a second conductivity type different from the first conductivity type and formed in a predetermined region of the semiconductor substrate. A pair of trenches are formed directly adjacent to respective opposite sides of the well region and have widths greater than those of respective depletion layers generated on the respective opposite sides so as to remove junction interfaces on the respective opposite sides. A depth of each trench from a surface of the semiconductor substrate is greater than that of a depletion layer generated on a bottom side of the well region. An insulating layer is buried in each of the trenches.

Abstract: Provided is a semiconductor device in which the drain region of the ESD protection NMOS transistor is electrically connected, through a drain extension region formed by an impurity diffusion region having the same conductivity as that of the drain region and arranged on both side surfaces and a bottom surface of the second trench isolation region which is formed next to the drain region, to the drain contact region formed by an impurity diffusion region having the same conductivity as that of the drain region.

Abstract: Provided is a semiconductor device in which the first trench isolation regions is placed between a substrate potential-fixing P-type diffusion region of an ESD protection NMOS transistor and source and drain regions of the ESD protection NMOS transistor, and has a depth greater than a depth of the second trench isolation region that is placed between a substrate potential-fixing P-type diffusion region of an NMOS transistor for internal circuit and source and drain regions of the NMOS transistor for internal circuit.

Abstract: Provided is a semiconductor device including an ESD protection N-MOS transistor isolated from another element by a shallow trench structure, in which the ESD protection N-MOS transistor includes a drain region on which a thin insulating film is formed, and an electrode which receives a signal from an external connection terminal is formed on the thin insulating film.

Abstract: A semiconductor device has a silicon substrate, an external connection terminal disposed on the silicon substrate, an internal circuit region disposed on the silicon substrate, an NMOS transistor for electrostatic discharge protection provided between the external connection terminal and the internal circuit region, and a wiring connecting together the external connection terminal and the NMOS transistor and connecting together the NMOS transistor and the internal circuit region. The NMOS transistor has a drain region and a gate electrode whose potential is fixed to a ground potential. The external connection terminal is smaller than the drain region and is formed above the drain region.

Abstract: Provided is a semiconductor device including an electrostatic discharge (ESD) protection element provided between an external connection terminal and an internal circuit region. In the semiconductor device, interconnect extending from the external connection terminal to the ESD protection element includes a plurality of metal interconnect layers so that a resistance of the interconnect extending from the external connection terminal to the ESD protection element is made smaller than a resistance of interconnect extending from the ESD protection element to an internal element. The interconnect extending from the ESD protection element to the internal element includes metal interconnect layers equal to or smaller in number than the plurality of interconnect layers used in the interconnect extending from the external connection terminal to the ESD protection element.

Abstract: A semiconductor device has a high voltage circuit section disposed on a semiconductor substrate having a first conductivity. The high voltage circuit section has a well region with a second conductivity, a first heavily doped impurity region with the first conductivity and disposed on the well region, a second heavily doped impurity region having a second conductivity and disposed on the semiconductor substrate, a trench isolation region disposed between the first and second heavily doped impurity regions, and an interconnect disposed over the trench isolation region. First and second electrodes are disposed above the trench isolation region, below the interconnect, and on opposite sides of a junction between the well region and the semiconductor substrate. The first electrode is disposed above the semiconductor substrate, and the second electrode is disposed above the well region.

Abstract: Provided is a semiconductor device, in which: patterns for detecting displacement at probing are formed of a plurality of minute conductors formed below a protective film; each of the plurality of minute conductors formed below the protective film is electrically insulated and formed to be smaller than a bottom surface of a tip of a probing needle used for carrying out an electrical measurement of IC chips; and the patterns for detecting displacement at probing are provided in a pair for each of the IC chips.

Abstract: Provided is a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection including drain regions connected with a first metal interconnect and source regions connected with another first metal interconnect alternately placed with each other, and gate electrodes each placed between each of the drain regions and each of the source regions, in which: at least one of the first metal interconnect and the other first metal interconnect being connected to a plurality of layers of metal interconnects other than the first metal interconnect; and the source regions include via-holes for electrically connecting the other first metal interconnect and the plurality of layers of metal interconnects other than the first metal interconnect, a greater number of the via-holes is formed as a distance of an interconnect connected to the NMOS transistor for ESD protection becomes larger.

Abstract: A MOS image sensor IC has a silicon substrate, a MOS transistor and photodiodes disposed on the silicon substrate, and pixel regions each comprising one of the photodiodes. A protective film is disposed around the pixel regions. A first conductor for potential fixation is disposed under the protective film and surrounds the pixel regions. The first conductor is electrically fixed to a potential of the silicon substrate.

Abstract: Provided is a semiconductor device having a trench isolation structure and a high power supply voltage circuit section including at least a well region and a MOS transistor formed therein. The high power supply voltage circuit section includes a carrier capture region for preventing latch-up in a vicinity of an end portion of the well region, and a depth of the carrier capture region is larger than a depth of the trench isolation region. The carrier capture region in the high power supply voltage circuit section is formed of a diffusion layer which is the same as that of a source or a drain region of the MOS transistor formed in the high power supply voltage circuit section.

Abstract: A semiconductor device comprises IC chips, each having semiconductor elements and pad regions, formed on a substrate, and conductor patterns for detecting displacement of a probe needle during a probing test of the IC chips. The conductor patterns each have an inner conductor and an outer conductor disposed in spaced-apart concentric relationship to one another, and the conductor patterns may be formed on the IC chips or on the substrate in a scribe region between adjacent IC chips. The distance between the inner and outer conductors is smaller than the size of the point or end tip of the probe needle. During a probing test, the probe needle is placed in contact with only the inner conductor, and slight displacement of the probe needle such that it moves into contact with both the inner and outer conductors during the probing test is detected by measuring an electricl characteristic between the two conductors so that corrective action can be taken.

Abstract: In a semiconductor device including, between an external connection terminal and an internal circuit region, an NMOS transistor for ESD protection having a gate potential fixed to a ground potential, the external connection terminal is formed above a drain region of the NMOS transistor for ESD protection, and the drain region is surrounded by a source region through a channel region. Further, the drain region has a shape with rounded corners in plan view.