Abstract: Provided is a semiconductor device, in which: patterns for detecting displacement at probing are formed of a plurality of minute conductors formed below a protective film; each of the plurality of minute conductors formed below the protective film is electrically insulated and formed to be smaller than a bottom surface of a tip of a probing needle used for carrying out an electrical measurement of IC chips; and the patterns for detecting displacement at probing are provided in a pair for each of the IC chips.

Abstract: Provided is a semiconductor device, in which: patterns for detecting displacement at probing are formed of a plurality of minute conductors formed below a protective film; each of the plurality of minute conductors formed below the protective film is electrically insulated and formed to be smaller than a bottom surface of a tip of a probing needle used for carrying out an electrical measurement of IC chips; and the patterns for detecting displacement at probing are provided in a pair for each of the IC chips.

Abstract: A semiconductor device has a silicon-on-insulator (SOI) substrate comprised of a silicon substrate, a buried insulating film disposed on the silicon substrate, and a single-crystal silicon device forming layer disposed on the buried insulating film. A bleeder resistor circuit comprises resistors each formed of the single-crystal silicon device forming layer. A MOS transistor has a thin gate oxide film disposed on the single-crystal silicon device forming layer and a gate electrode disposed on the thin gate oxide film. Electrodes are disposed over the respective resistors for fixing a resistance of the resistors, the electrodes being made of the same material as that of the gate electrode of the MOS transistor. Impurity diffusion regions are disposed under the respective resistors and in the silicon substrate for fixing the resistance of the resistors.

Abstract: A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. The third region and the second region are in contact with each other and make a low resistance junction. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode.

Abstract: Provided is a semiconductor device including an electrostatic discharge (ESD) protection element provided between an external connection terminal and an internal circuit region. In the semiconductor device, interconnect extending from the external connection terminal to the ESD protection element includes a plurality of metal interconnect layers so that a resistance of the interconnect extending from the external connection terminal to the ESD protection element is made smaller than a resistance of interconnect extending from the ESD protection element to an internal element. The interconnect extending from the ESD protection element to the internal element includes metal interconnect layers equal to or smaller in number than the plurality of interconnect layers used in the interconnect extending from the external connection terminal to the ESD protection element.

Abstract: In a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection surrounded by a shallow trench for device isolation, in order to suppress the off-leak current in an off state, there is formed, in the vicinity of the drain region of the NMOS transistor for ESD protection, an n-type region receiving a signal from an external connection terminal via a p-type region in contact with the drain region of the NMOS transistor for ESD protection.

Abstract: In order to suppress an off leak current of an off transistor for ESD protection, in an NMOS for ESD protection whose isolation region has a shallow trench structure, a drain region is placed apart from the shallow trench isolation region so as not to be in direct contact with the shallow trench isolation region in a region where the drain region of the NMOS transistor for ESD protection is adjacent to at least a gate electrode of the NMOS transistor for ESD protection.

Abstract: Provided is a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection including drain regions connected with a first metal interconnect and source regions connected with another first metal interconnect alternately placed with each other, and gate electrodes each placed between each of the drain regions and each of the source regions, in which: at least one of the first metal interconnect and the other first metal interconnect being connected to a plurality of layers of metal interconnects other than the first metal interconnect; and the source regions include via-holes for electrically connecting the other first metal interconnect and the plurality of layers of metal interconnects other than the first metal interconnect, a greater number of the via-holes is formed as a distance of an interconnect connected to the NMOS transistor for ESD protection becomes larger.

Abstract: Provided is a semiconductor device, including: an N-type MOS transistor for an internal element and a P-type MOS transistor for an internal element both provided in an internal circuit region; and an N-type MOS transistor for ESD protection provided between an external connection terminal and the internal circuit region, in which a gate electrode of the N-type MOS transistor for ESD protection is formed of P-type polysilicon.

Abstract: A semiconductor device has a trench isolation structure and a high voltage circuit section including at least one well region, a MOS transistor, and an interconnect for electrically connecting elements. An electrode for preventing inversion layer formation is formed in a region above the trench isolation region provided near an end portion of the well region and below the interconnect for preventing parasitic formation of an inversion layer on a surface of the semiconductor substrate due to the potential of the interconnect, and fixed at the same potential as that of the semiconductor substrate therebelow. Further, a guard ring region formed of a heavily doped impurity region of the same conductivity type as the semiconductor substrate is provided below the electrode for preventing inversion layer formation and is fixed at the same potential as that of the semiconductor substrate to capture carriers to prevent latch-up.

Abstract: Provided is a semiconductor device having a trench isolation structure and a high power supply voltage circuit section including at least a well region and a MOS transistor formed therein. The high power supply voltage circuit section includes a carrier capture region for preventing latch-up in a vicinity of an end portion of the well region, and a depth of the carrier capture region is larger than a depth of the trench isolation region. The carrier capture region in the high power supply voltage circuit section is formed of a diffusion layer which is the same as that of a source or a drain region of the MOS transistor formed in the high power supply voltage circuit section.

Abstract: Polycrystalline silicon thin films are each fixed to the same potential and are each formed under the protective film of each of a plurality of pixel regions for receiving red light, a plurality of pixel regions for receiving green light, and a plurality of pixel regions for receiving blue light, and each polycrystalline silicon thin films has a different thickness for selectively transmitting a received light wavelength of each of the plurality of pixel regions for receiving red light, the plurality of pixel regions for receiving green light, and the plurality of pixel regions for receiving blue light to function as a color filter. The color filter can be formed during an IC manufacturing process while the color filter is positioned to align with the pixel region serving as a light receiving element, with higher precision.

Abstract: Provided is an image sensor IC in which a conductive material transmissive to light, which is fixed to the same potential, is formed under a protection film in a plurality of pixel regions. The conductive material transmissive to light for potential fixation is formed in each pixel, has a narrow and linear shape, and is electrically connected so as to hold the same potential as a potential of a silicon substrate. Accordingly, a potential of each of the regions which become a base at the time of forming the protective film is kept constant in an entire pixel region, thereby obtaining a uniform thickness and quality of the protective film. As a result, variation in photoelectric conversion characteristic of the pixels can be eliminated.

Abstract: Provided is a semiconductor device, in which: patterns for detecting displacement at probing are formed of a plurality of minute conductors formed below a protective film; each of the plurality of minute conductors formed below the protective film is electrically insulated and formed to be smaller than a bottom surface of a tip of a probing needle used for carrying out an electrical measurement of IC chips; and the patterns for detecting displacement at probing are provided in a pair for each of the IC chips.

Abstract: Patterns for detecting displacement at probing occupying a small area are provided and are capable of detecting the direction of the displacement when a needle is displaced in probing. The patterns for detecting displacement at probing are arranged in pairs in a scribe region adjacent to IC chips, the pattern for detecting displacement at probing is formed of an inner conductor and an outer conductor arranged at a minute distance from the inner conductor which are concentrically formed, and the outer conductor is divided into a plurality of parts.

Abstract: Provided is a MOS image sensor IC in which: conductors for potential fixation, each fixed to the same potential, surround a plurality of pixel regions; the conductors for potential fixation are each formed in a narrow shape in the pixel regions, and are electrically connected to each other so that the conductors have the potential of a silicon substrate. Accordingly, each potential of the entire pixel regions, which are formed under a protective film when a protective film is formed, is made constant, thereby obtaining a uniform thickness and quality of the protective film, which can suppress a variation in photoelectric conversion characteristic of pixels.

Abstract: A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film formed on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor thin film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. A conductive thin film is connected with the second region and the third region. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode.

Abstract: Provided is a semiconductor device for performing photoelectric conversion of incident light, including: a p-type substrate (1), an n-type well (2) having a predetermined depth and formed in a predetermined region of the p-type substrate (1), and a depletion layer generated at a junction interface between the p-type substrate (1) and the n-type well (2). In the trenches (22) having a depth larger than that of a depletion layer (K1) generated on a bottom side of the n-type well (2) and a width larger than that of depletion layers (K2, K3) generated on sides of the n-type well (2) are provided so as to remove junction interfaces (J2, J3) on the sides of the n-type well (2), and an insulating layer (21) is buried in the trenches (22).

Abstract: Provided is a semiconductor device having a semiconductor integrated circuit formed on an SOI substrate, in which a bleeder resistor is formed of a single-crystal-silicon device-forming layer, and an upper electrode for resistance fixation is formed over the bleeder resistor and on a thin oxide film and is fixed to the identical potential as that of the bleeder resistor located below the electrode. Further, an impurity diffusion region is formed on the silicon substrate, and is fixed to the identical potential as that of the bleeder resistor above the impurity diffusion region. In addition, those three elements; the upper electrode for resistance fixation, the bleeder resistor, and the lower impurity diffusion region are collectively and electrically connected with one another through a conductor filling a contact hole for potential fixation.

Abstract: A semiconductor device is constituted by a P-type thin film resistor formed of a P-type semiconductor thin film and an N-type thin film resistor formed of an N-type semiconductor thin film, in order to avoid variation in resistance in the case of stress application. Further, a structure is adopted in which the P-type thin film resistor and the N-type thin film resistor are laminated vertically in a contact manner or arranged horizontally in a contact manner. Also, the P-type thin film resistor and the N-type thin film resistor share a contact region at the end of a resistor, which defines a unit resistance in the bleeder resistor circuit.