Patents by Inventor Hiroaki Takasu

Hiroaki Takasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050106830
    Abstract: There are provided a bleeder resistance circuit which has an accurate voltage dividing ratio, a small temperature coefficient of a resistance value, and high precision, and a semiconductor device using such a bleeder resistance circuit, which has high precision and a small temperature coefficient, such as a voltage detector or a voltage regulator. In the bleeder resistance circuit using a thin film resistor, conductors located over and under the thin film resistor are made to have substantially the same potential as the thin film resistor. Further, when polysilicon is used for the thin film resistor, the film thickness of the polysilicon thin film resistor is thinned, and an impurity introduced into the polysilicon thin film resistor is made to be a P-type. Thus, a variation in a resistance value is suppressed, and a temperature dependency of the resistance value is made small.
    Type: Application
    Filed: December 3, 2004
    Publication date: May 19, 2005
    Inventors: Mika Shiiki, Hiroaki Takasu
  • Patent number: 6844599
    Abstract: A semiconductor device has thin film resistors connected in series to form a bleeder resistance circuit. Each of the thin film resistors is made of a polysilicon film doped with B or BF2 P-type impurities and has two end portions each having a high impurity concentration region. A first insulating film overlies the thin film resistors. First conductors are connected to the ends of the thin film resistors for connecting the thin film resistors in series. The semiconductor device has second conductors each connected to a respective one of the first conductors and overlying a respective one of the thin film resistors through the first insulating film.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: January 18, 2005
    Assignee: Seiko Instruments Inc.
    Inventors: Mika Shiiki, Hiroaki Takasu
  • Patent number: 6803886
    Abstract: An object of the present invention is to provide an improved structure of highly fine bight valve device. On a quartz glass substrate 1 and a monocrystalline silicon thin film layer z bonded on the quartz glass substrate 2, are provided an X diving circuit 6 and a Y driving circuit 8 integrated by a very large scale integration process, driving electrodes 5 of a matrix type for conduction signals outputted from the X driving circuit 6 and the Y driving circuit 8, a transistor 9 and a display pixel electrode 10 arranged at a cross-section of the driving electrodes 5 of a matrix type, a control circuit 4 for supplying timing signals to the X driving circuit 6 and the Y driving circuit 8, and a display data generating circuit 3 for generating display data in order to display an image, and further a light source element driving circuit 19 for driving a light source element is provided thereon.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: October 12, 2004
    Assignee: Seiko Instruments Inc.
    Inventors: Kenichi Kondo, Kunihiro Takahashi, Hiroaki Takasu, Tsuneo Yamazaki, Atsushi Sakurai
  • Patent number: 6653688
    Abstract: A semiconductor device comprises a MOS transistor and a resistor. The resistor has a P-type resistor formed from a P-type semiconductor, an N-type resistor formed from an N-type semiconductor and disposed adjacent the P-type resistor, and an insulating film disposed between the P-type and N-type resistors. The P-type resistor is arranged at the low potential side of the semiconductor device and the N-type resistor is arranged at the high potential side thereof. A portion of the insulating film between the P-type and N-type resistors is made electrically conductive by irradiating the portion with a laser beam to destroy the insulating property thereof to thereby achieve conductivity between the P-type and N-type resistors. A gate electrode of the MOS transistor is formed of a P-type polysilicon thin film having the same high concentration impurity as that of the region where the P-type resistor is in contact with a metal wiring, thereby enhancing the current driving capacity of a driver MOS.
    Type: Grant
    Filed: April 3, 2002
    Date of Patent: November 25, 2003
    Assignee: Seiko Instruments Inc.
    Inventors: Hiroaki Takasu, Jun Osanai
  • Patent number: 6653713
    Abstract: A thin film resistor maintains its resistance value when stress is applied so that it may be used in a high precision bleeder resistor circuit to maintain an accurate voltage dividing ratio. The thin film resistor has a P-type thin film resistor formed of a P-type semiconductor thin film and an N-type thin film resistor formed of an N-type semiconductor thin film overlapping the P-type thin film resistor with an insulating layer interposed therebetween, so that a change in resistance value when stress is applied is prevented. In a bleeder resistor circuit, a resistance value of one unit is regulated by a resistance value formed by a combination of the P-type thin film resistor and the N-type thin film resistor so that an accurate voltage dividing ratio can be maintained when stress is applied.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: November 25, 2003
    Assignee: Seiko Instruments Inc.
    Inventor: Hiroaki Takasu
  • Patent number: 6586282
    Abstract: A method of manufacturing a semiconductor device comprises forming a thin film over a semiconductor substrate, patterning the thin film to define a portion of a laser trimming registration position pattern while simultaneously forming a fuse element formed from the same thin film and separate from the portion of the laser trimming position registration pattern, and forming a metallic film on the portion of the laser trimming position pattern but not on the fuse element.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: July 1, 2003
    Assignee: Seiko Instruments Inc.
    Inventor: Hiroaki Takasu
  • Patent number: 6566721
    Abstract: It is intended to provide a semiconductor device in which a fuse required conventionally is omitted and an initial resistance value can be maintained even under stress imposed due to packaging or the like, a high-accuracy bleeder resistance circuit that can maintain an accurate voltage division ratio, and a high-accuracy semiconductor device with such a bleeder resistance circuit, for example, a voltage detector or a voltage regulator. In a semiconductor device with a resistor, the resistor includes a P-type resistor made of a P-type semiconductor and an N-type resistor made of an N-type semiconductor which are combined to form one body, and the P-type resistor and the N-type resistor are placed on low and high potential sides, respectively. The P-N junction is irradiated with a laser beam or the like, whereby rectification is damaged to allow conduction.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: May 20, 2003
    Assignee: Seiko Instruments Inc.
    Inventor: Hiroaki Takasu
  • Publication number: 20030052373
    Abstract: The present invention relates to a field effect transistor formed on a semiconductor thin film formed on an insulating substrate, and to an integrated circuit thereof. Provided is a structure such that a maximum allowable voltage in an output voltage is improved and a bipolar transistor is attained. A field effect transistor according to the present invention employs a structure in which a body contact region is interposed between source regions in order to realize a higher maximum allowable voltage with a smaller area. In order to realize the bipolar transistor with an increased channel width without external wirings for fixing a body potential, a structure of a transistor is also formed in which a drain/source region, a first gate electrode, a portion where a body contact region is arranged with a second region having a first conductivity type, a second gate electrode, and a source/drain region are arranged.
    Type: Application
    Filed: August 27, 2002
    Publication date: March 20, 2003
    Inventors: Yutaka Hayashi, Hisashi Hasegawa, Hiroaki Takasu, Jun Osanai
  • Publication number: 20030025659
    Abstract: An object of the present invention is to provide an improved structure of highly fine bight valve device.
    Type: Application
    Filed: August 17, 2001
    Publication date: February 6, 2003
    Applicant: SEIKO INSTRUMENTS INC.
    Inventors: Kenichi Kondo, Kunihiro Takahashi, Hiroaki Takasu, Tsuneo Yamazaki, Atsushi Sakurai
  • Patent number: 6492236
    Abstract: There is provided a manufacturing method for obtaining an MOS transistor which has a homopolar gate structure and a high-melting metallic silicide structure and is suitable even for high speed operation, while at the same time having a structure in which a sufficient withstand voltage can be attained by forming, by a simple method, low concentration drain regions with a long distance. A source and a drain, which have a low concentration, are formed and a thick insulating film and positive resist is formed (applied) on a gate electrode. Then, the positive resist is exposed at an amount of exposure suitable to expose a portion corresponding to a film thickness of the positive resist formed on a flat portion of the thick insulating film as a base and developed. The thick insulating film is etched by an amount substantially corresponding to a film thickness thereof by anisotropic etching using as a mask those portions of the positive resist partially remaining in a step portion.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: December 10, 2002
    Assignee: Seiko Instruments Inc.
    Inventors: Hiroaki Takasu, Jun Osanai
  • Patent number: 6489662
    Abstract: A semiconductor integrated circuit device comprises a thin film layer formed on a silicon-on-insulator (SOI) substrate, a laser-trimmable fuse element, a laser trimming positioning pattern for facilitating trimming of the fuse element, a high speed MOS transistor of a complete depletion type, and a high withstand voltage type MOS transistor and an ESD protecting circuit region connected to the high speed MOS transistor to prevent electrostatic breakdown of the thin film layer.
    Type: Grant
    Filed: April 27, 2000
    Date of Patent: December 3, 2002
    Assignee: Seiko Instruments Inc.
    Inventor: Hiroaki Takasu
  • Publication number: 20020163047
    Abstract: It is intended to provide a semiconductor device in which a fuse required conventionally is omitted and an initial resistance value can be maintained even under stress imposed due to packaging or the like, a high-accuracy bleeder resistance circuit that can maintain an accurate voltage division ratio, and a high-accuracy semiconductor device with such a bleeder resistance circuit, for example, a voltage detector or a voltage regulator. In a semiconductor device with a resistor, the resistor includes a P-type resistor made of a P-type semiconductor and an N-type resistor made of an N-type semiconductor which are combined to form one body, and the P-type resistor and the N-type resistor are placed on low and high potential sides, respectively. The P-N junction is irradiated with a laser beam or the like, whereby rectification is damaged to allow conduction.
    Type: Application
    Filed: October 19, 2001
    Publication date: November 7, 2002
    Inventor: Hiroaki Takasu
  • Publication number: 20020153568
    Abstract: Provided are a semiconductor device in which a fuse that has been necessary in a conventional manner is removed and an initial resistance value can be maintained even when stress is applied by packaging or the like, a high-precision bleeder resistance circuit capable of maintaining an accurate voltage division ratio, and a high-precision semiconductor device that employs the bleeder resistance circuit, such as a voltage detector or a voltage regulator. The semiconductor device including a resistor is characterized in that: the resistor has such a construction that a P-type resistor formed from a P-type semiconductor and an N-type resistor formed from an N-type semiconductor are integrated via an insulating film; the P-type resistor is disposed at a low potential side and the N-type resistor is disposed at a high potential side; and a laser beam or the like is irradiated to the insulating film portion to destroy insulating property to thereby achieve conductivity between the P-type and N-type resistors.
    Type: Application
    Filed: April 3, 2002
    Publication date: October 24, 2002
    Inventors: Hiroaki Takasu, Jun Osanai
  • Publication number: 20020151144
    Abstract: There is provided a manufacturing method for obtaining an MOS transistor which has a homopolar gate structure and a high-melting metallic silicide structure and is suitable even for high speed operation, while at the same time having a structure in which a sufficient withstand voltage can be attained by forming, by a simple method, low concentration drain regions with a long distance. A source and a drain, which have a low concentration, are formed and a thick insulating film and positive resist is formed (applied) on a gate electrode. Then, the positive resist is exposed at an amount of exposure suitable to expose a portion corresponding to a film thickness of the positive resist formed on a flat portion of the thick insulating film as a base and developed. The thick insulating film is etched by an amount substantially corresponding to a film thickness thereof by anisotropic etching using as a mask those portions of the positive resist partially remaining in a step portion.
    Type: Application
    Filed: March 12, 2002
    Publication date: October 17, 2002
    Inventors: Hiroaki Takasu, Jun Osanai
  • Publication number: 20020145176
    Abstract: A semiconductor device is provided: which is formed with an analog IC with high precision in which a complete depletion type high speed MOS transistor and a high pressure-resistance MOS transistor are mixedly mounted on an SOI substrate; which is resistant to ESD breakdown; in which a crack or peel is prevented in a dicing process; and in which trimming positioning precision is improved to enable cost-down. A laser trimming fuse element and a bleeder resistance are formed of a single crystal silicon device forming layer on the SOI substrate. The complete depletion type high speed MOS transistor, the high pressure-resistance MOS transistor, and an ESD protection element are formed in the single crystal silicon device forming layer, and the thickness of the single crystal silicon device forming layer of the complete depletion type high speed MOS transistor region is made thinner than that of the single crystal silicon device forming layer of other region.
    Type: Application
    Filed: March 12, 2002
    Publication date: October 10, 2002
    Inventors: Hiroaki Takasu, Jun Osanai
  • Publication number: 20020145177
    Abstract: A semiconductor device is provided: which is formed with an analog IC with high precision in which a complete depletion type high speed MOS transistor and a high pressure-resistance MOS transistor are mixedly mounted on an SOI substrate; which is resistant to ESD breakdown; in which a crack or peel is prevented in a dicing process; and in which trimming positioning precision is improved to enable cost-down. A laser trimming fuse element and a bleeder resistance are formed of a single crystal silicon device forming layer on the SOI substrate. The complete depletion type high speed MOS transistor and the high pressure-resistance MOS transistor are formed in the single crystal silicon device forming layer, and the thickness of the single crystal silicon device forming layer of the complete depletion type high speed MOS transistor region is made thin.
    Type: Application
    Filed: March 12, 2002
    Publication date: October 10, 2002
    Inventors: Hiroaki Takasu, Jun Osanai
  • Patent number: 6441461
    Abstract: A thin film resistor element which maintains its resistance value when stress is applied such as during packaging, so that the resistor element may be used in a high precision bleeder resistor circuit to maintain an accurate voltage dividing ratio. The thin film resistor element has a P-type thin film resistor formed of a P-type semiconductor thin film and an N-type thin film resistor formed of an N-type semiconductor thin film, so that a change in resistance value when stress is applied is prevented. In a bleeder resistor circuit, a resistance value of one unit is regulated by a resistance value formed by a combination of the P-type thin film resistor and the N-type thin film resistor so that, even in the case where stress is applied, a change in resistance values of the respective resistor elements cancel out each other and an accurate voltage dividing ratio can be maintained.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: August 27, 2002
    Assignee: Seiko Instruments Inc.
    Inventor: Hiroaki Takasu
  • Publication number: 20020096739
    Abstract: There is provided a semiconductor device in which an initial resistance value can be kept even in the case where stress is applied by packaging or the like. A thin film resistor of the semiconductor device is composed of a P-type thin film resistor made from a P-type semiconductor thin film and an N-type thin film resistor made from an N-type semiconductor thin film. Thus, a variation in a resistance value in the case where the stress is applied is prevented. Also, in a bleeder resistance circuit, a resistance value as one unit is defined by a resistance value obtained by a lamination of the P-type thin film resistor and the N-type thin film resistor. Therefore, even if the stress is applied, variations in resistance values of respective resistors are cancelled and thus an accurate voltage dividing ratio can be kept. Further, an area of the bleeder resistance circuit can be reduced.
    Type: Application
    Filed: October 12, 2001
    Publication date: July 25, 2002
    Inventor: Hiroaki Takasu
  • Publication number: 20020084487
    Abstract: A semiconductor device in which analog ICs are formed having a mixture of complete depletion high speed MOS transistors and high endurance MOS transistors on an SOI substrate, and which is strong with respect to ESD destruction, is provided. A laser trimming position determining pattern is constituted of a region having high light reflectivity and a region having low light reflectivity. The high light reflectivity region is formed by a high light reflectivity film on a level base, and the low light reflectivity region is formed by the high light reflectivity film formed on a lattice pattern, a stripe pattern, or a dot pattern for diffused reflection of light, which is formed of the same polycrystalline silicon film as a laser trimming fuse element.
    Type: Application
    Filed: October 12, 2001
    Publication date: July 4, 2002
    Inventor: Hiroaki Takasu
  • Publication number: 20020047183
    Abstract: There are provided a bleeder resistance circuit which has an accurate voltage dividing ratio, a small temperature coefficient of a resistance value, and high precision, and a semiconductor device using such a bleeder resistance circuit, which has high precision and a small temperature coefficient, such as a voltage detector or a voltage regulator. In the bleeder resistance circuit using a thin film resistor, conductors located over and under the thin film resistor are made to have substantially the same potential as the thin film resistor. Further, when polysilicon is used for the thin film resistor, the film thickness of the polysilicon thin film resistor is thinned, and an impurity introduced into the polysilicon thin film resistor is made to be a P-type. Thus, a variation in a resistance value is suppressed, and a temperature dependency of the resistance value is made small.
    Type: Application
    Filed: July 27, 2001
    Publication date: April 25, 2002
    Inventors: Mika Shiiki, Hiroaki Takasu