Patents by Inventor Hirofumi Yamashita

Hirofumi Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240340016
    Abstract: An analog signal generation device according to the present invention includes a DA converter that adjusts a signal level of a digital signal according to a DAC correction amount and then converts the digital signal into an analog signal, a detector that detects the analog signal and outputs a detection signal, a storage unit that stores a characteristic equation for calculating the DAC correction amount, and a control unit, in which in a case where the differential voltage when the digital signal having a signal level of a predetermined value is input to the DA converter is larger than a threshold value, the control unit calculates a new DAC correction amount based on the differential voltage by using the characteristic equation, and in a case where the differential voltage does not fall within the threshold value, the control unit corrects the characteristic equation.
    Type: Application
    Filed: March 26, 2024
    Publication date: October 10, 2024
    Inventors: Hirofumi ONO, Koji YAMASHITA
  • Patent number: 12111921
    Abstract: Systems, methods, and other embodiments described herein relate to improving incident response within a vehicle environment. In one embodiment, a method includes, responsive to detecting an attack on a threatened component of a computing system, gathering information about the threatened component, including at least a dependency list that specifies related components to the threatened component. The method includes determining a risk score for the attack according to a risk level associated with the attack, a risk type of the threatened component, and combined risks associated with compromising the related components. The method includes providing a report specifying information about the attack, including at least the risk score.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: October 8, 2024
    Assignee: Denso Corporation
    Inventors: Carlos Mora-Golding, Ameer Kashani, Gopalakrishnan Iyer, Hirofumi Yamashita
  • Publication number: 20240327191
    Abstract: A remaining amount detection apparatus detects a remaining amount of a beverage in a beverage barrel connected to a beverage server. The remaining amount detection apparatus includes a pressure sensor configured to detect a pressure in a channel for supplying a carbon dioxide gas to the beverage barrel, and a controller configured to obtain the remaining amount of the beverage based on a change of a detected pressure that is the pressure detected by the pressure sensor. The controller obtains the remaining amount based on a time ti between a first time tt1 at which a decrease amount of the detected pressure is larger than a first reference value R1 and a second time tt2 at which after the first time tt1, an increase amount from a minimum value Pmin after the detected pressure takes the minimum value Pmin is larger than a second reference value R2.
    Type: Application
    Filed: June 12, 2024
    Publication date: October 3, 2024
    Inventors: Naoyuki YAMASHITA, Hirofumi IMAI, Kazuya SHIRAISHI, Hisashi UCHIDA
  • Publication number: 20240327193
    Abstract: A carbon dioxide gas supply apparatus 100 includes a pressure adjuster 10 configured to adjust a pressure of a carbon dioxide gas supplied from a carbon dioxide gas supply source 3 to a primary-side port P1 and send the carbon dioxide gas from a secondary-side port P2; a relief valve 20 connected to a first channel PH1 configured to connect the secondary-side port P2 and a beverage barrel 1; and a controller 30 configured to control the pressure adjuster 10 and the relief valve 20. The controller 30 controls the relief valve 20 such that a pressure in the first channel PH1 is reduced in accordance with an output of a temperature sensor 81 configured to detect a temperature of a beverage sent from the beverage barrel 1 to a beverage server 2.
    Type: Application
    Filed: June 12, 2024
    Publication date: October 3, 2024
    Inventors: Naoyuki YAMASHITA, Hirofumi IMAI, Kazuya SHIRAISHI, Hisashi UCHIDA
  • Publication number: 20240331467
    Abstract: A log management device acquires an alive monitoring log indicating that a security sensor of an electronic control unit mounted on a vehicle is operating; records acquisition of the alive monitoring log in an alive monitoring table; identifies an unacquired alive monitoring log, and records, in the alive monitoring table, an unacquired period during which the unacquired alive monitoring log is not acquired; and invalidates a record of the unacquired alive monitoring log in the alive monitoring table when the unacquired period of the unacquired alive monitoring log is equal to or longer than a predetermined period.
    Type: Application
    Filed: March 16, 2024
    Publication date: October 3, 2024
    Inventors: Shogo WATANABE, Tokuya INAGAKI, Ryosuke MURAKAMI, Hirofumi YAMASHITA, Shinnosuke SUGAWARA, Takeshi MATSUI
  • Publication number: 20240313014
    Abstract: A decrease in charge transfer efficiency is suppressed. An imaging apparatus according to an embodiment includes a plurality of pixels arrayed in a two-dimensional lattice pattern, in which each of the pixels includes a photoelectric conversion unit (PD) that photoelectrically converts incident light, a gate electrode that transfers charge accumulated in the photoelectric conversion unit, and a diffusion region (FD) to which the charge transferred from the photoelectric conversion unit flows, and the photoelectric conversion unit, the gate electrode, and the diffusion region are arrayed in a semiconductor substrate along a substrate thickness direction of the semiconductor substrate.
    Type: Application
    Filed: March 25, 2022
    Publication date: September 19, 2024
    Applicants: SONY SEMICONDUCTOR SOLUTIONS CORPORATION, SONY GROUP CORPORATION
    Inventors: Hirokazu OKABE, Hirofumi YAMASHITA
  • Patent number: 12074580
    Abstract: A signal generation unit 2, a DA converter 3, variable attenuators 40, 42, 44, and 46, a measurement unit 6 that detects a level of the signal attenuated by the variable attenuators 40, 42, 44, and 46 and passed through one or more semiconductor components, a switch 48 that switches between an Internal path through which the signal attenuated by the variable attenuator 40, 42, 44, and 46 is transmitted to the measurement unit 6 and an External path through which the signal attenuated by the variable attenuator 40, 42, 44, and 46 is output from an output terminal 10, and a control unit 7 that obtains a correction value of an attenuation amount of the variable attenuators 40, 42, and 44 with the Internal path and obtains a correction value of an attenuation amount of the variable attenuator 46 with the External path.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: August 27, 2024
    Assignee: ANRITSU CORPORATION
    Inventors: Hirofumi Ono, Koji Yamashita, Shinichi Ito
  • Patent number: 12074651
    Abstract: A signal generation unit 2, a DA converter 3, variable attenuators 40, 42, 44, and 46 that attenuate an analog signal converted by the DA converter 3, a measurement unit 6 that detects a level of the signal attenuated by the variable attenuators 40, 42, 44, and 46 and passed through one or more semiconductor components, and a control unit 7 that obtains a value of a step error, which is a correction value of an attenuation amount of the variable attenuators 40, 42, 44, and 46 in each of a plurality of steps obtained by dividing a maximum value of the attenuation amount of the variable attenuators 40, 42, 44, and 46 by a variation amount, which is a predetermined attenuation amount are included.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: August 27, 2024
    Assignee: ANRITSU CORPORATION
    Inventors: Hirofumi Ono, Koji Yamashita, Shinichi Ito
  • Publication number: 20240266381
    Abstract: An imaging element according to an embodiment of the present disclosure includes a first semiconductor substrate, and a second semiconductor substrate stacked over the first semiconductor substrate with an insulating layer interposed therebetween. The first semiconductor substrate includes a photoelectric conversion section, and a charge-holding section that holds charges transferred from the photoelectric conversion section. The second semiconductor substrate includes an amplification transistor that generates a signal of a voltage corresponding to a level of charges held in the charge-holding section. The amplification transistor includes a channel region, a source region, and a drain region in a plane intersecting a front surface of the second semiconductor substrate, and includes a gate electrode being opposed to the channel region with a gate insulating film interposed therebetween and being electrically coupled to the charge-holding section.
    Type: Application
    Filed: April 15, 2024
    Publication date: August 8, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shinichi MIYAKE, Hirofumi YAMASHITA
  • Patent number: 12027562
    Abstract: An imaging element according to an embodiment of the present disclosure includes a first semiconductor substrate, and a second semiconductor substrate stacked over the first semiconductor substrate with an insulating layer interposed therebetween. The first semiconductor substrate includes a photoelectric conversion section, and a charge-holding section that holds charges transferred from the photoelectric conversion section. The second semiconductor substrate includes an amplification transistor that generates a signal of a voltage corresponding to a level of charges held in the charge-holding section. The amplification transistor includes a channel region, a source region, and a drain region in a plane intersecting a front surface of the second semiconductor substrate, and includes a gate electrode being opposed to the channel region with a gate insulating film interposed therebetween and being electrically coupled to the charge-holding section.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: July 2, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Shinichi Miyake, Hirofumi Yamashita
  • Publication number: 20240213286
    Abstract: A light detecting device includes a semiconductor layer having a first surface and a second surface located on opposite sides to each other in a thickness direction, and a photoelectric conversion cell provided in the semiconductor layer and partitioned by a first isolation region. The photoelectric conversion cell includes a first photoelectric conversion region adjacent to a second photoelectric conversion region in plan view and each having a photoelectric conversion unit and a transfer transistor, a second isolation region arranged between the first photoelectric conversion region and the second photoelectric conversion region in plan view and extending in a thickness direction of the semiconductor layer, and an element formation region partitioned on the first surface side of the semiconductor layer by a third isolation region and provided with a pixel transistor. The element formation region extends over the first and second photoelectric conversion regions in plan view.
    Type: Application
    Filed: February 13, 2024
    Publication date: June 27, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hirofumi YAMASHITA, Chihiro TOMITA, Harumi TANAKA
  • Publication number: 20240213288
    Abstract: Alight detecting device includes a semiconductor layer having a first surface and a second surface located on opposite sides to each other in a thickness direction, and a photoelectric conversion cell provided in the semiconductor layer and partitioned by a first isolation region. The photoelectric conversion cell includes a first photoelectric conversion region adjacent to a second photoelectric conversion region in plan view and each having a photoelectric conversion unit and a transfer transistor, a second isolation region arranged between the first photoelectric conversion region and the second photoelectric conversion region in plan view and extending in a thickness direction of the semiconductor layer, and an element formation region partitioned on the first surface side of the semiconductor layer by a third isolation region and provided with a pixel transistor. The element formation region extends over the first and second photoelectric conversion regions in plan view.
    Type: Application
    Filed: March 4, 2024
    Publication date: June 27, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hirofumi YAMASHITA, Chihiro TOMITA, Harumi TANAKA
  • Publication number: 20240121529
    Abstract: To provide a solid-state imaging device and an electronic apparatus capable of achieving both of a high dynamic range operation and an auto focus operation in a pixel configuration in which a plurality of unit pixels includes two or more subpixels. There is provided a solid-state imaging device including: a first pixel separation region that separates a plurality of unit pixels including two or more subpixels; a second pixel separation region that separates each of the plurality of unit pixels separated by the first pixel separation region; and an overflow region that causes signal charges accumulated in the subpixels to overflow to at least one of adjacent subpixels, in which the overflow region is formed between a first subpixel and a second subpixel.
    Type: Application
    Filed: December 19, 2023
    Publication date: April 11, 2024
    Inventors: HIROFUMI YAMASHITA, SHOHEI SHIMADA, YUSUKE OTAKE, YUSUKE TANAKA, TOSHIFUMI WAKANO
  • Patent number: 11948963
    Abstract: Provided is an imaging apparatus including an imaging unit having a plurality of pixels, the pixels each having: a conversion element converting incident light into photoelectrons; a floating diffusion layer electrically connected to the conversion element and converting the photoelectrons into a voltage signal; a differential amplifier circuit electrically connected to the floating diffusion layer, including an amplifier transistor to which a potential of the floating diffusion layer is input, and amplifying the potential of the floating diffusion layer; a feedback transistor electrically connected to the amplifier transistor and initializing the differential amplifier circuit; a clamp capacitance connected in series between the floating diffusion layer and the amplifier transistor; and a reset transistor connected in parallel between the floating diffusion layer and the clamp capacitance and initializing the potential of the floating diffusion layer.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: April 2, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Hirofumi Yamashita
  • Patent number: 11937002
    Abstract: Provided is a solid-state imaging device and an electronic apparatus capable of achieving both of a high dynamic range operation and an auto focus operation in a pixel configuration in which a plurality of unit pixels includes two or more subpixels. The solid-state imaging device includes a first pixel separation region that separates a plurality of unit pixels including two or more subpixels, a second pixel separation region that separates each of the plurality of unit pixels separated by the first pixel separation region and an overflow region that causes signal charges accumulated in the subpixels to overflow to at least one of adjacent subpixels, in which the overflow region is formed between a first subpixel and a second subpixel.
    Type: Grant
    Filed: November 8, 2022
    Date of Patent: March 19, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hirofumi Yamashita, Shohei Shimada, Yusuke Otake, Yusuke Tanaka, Toshifumi Wakano
  • Patent number: 11890298
    Abstract: To develop a novel administration method of a fucoidan-containing hair-growing agent and to provide a means for exerting excellent effects of a fucoidan. A hair-growing agent of the present invention is characterized in that it is composed of a combination of a fucoidan-containing microneedle and a fucoidan-containing liniment. A base of the fucoidan-containing microneedle is preferably a biosoluble polymer. A hair-growing method of the present invention is characterized in that the fucoidan-containing microneedle and the fucoidan-containing liniment are concomitantly used.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: February 6, 2024
    Assignee: COSMED PHARMACEUTICAL CO., LTD.
    Inventors: Ying-shu Quan, Hirofumi Yamashita, Fumio Kamiyama, Akira Yamamoto, Hidemasa Katsumi
  • Patent number: 11893394
    Abstract: Systems, methods, and other embodiments described herein relate to validating programs of a computing system in a vehicle by tracking a boot sequence. In one embodiment, a method includes, responsive to detecting initiation of a boot sequence in a computing system, tracking characteristics of programs executing as part of the boot sequence. The method includes determining whether the programs correspond with a program execution graph (PEG) by comparing the characteristics of the programs as the programs boot with the PEG. The method includes providing a response to thwart a malicious program when the boot sequence does not match the PEG.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: February 6, 2024
    Assignee: DENSO CORPORATION
    Inventors: Carlos Mora-Golding, Ameer Kashani, Gopalakrishnan Iyer, Hirofumi Yamashita
  • Publication number: 20240038815
    Abstract: A light detecting device includes a semiconductor layer having a first surface and a second surface located on opposite sides to each other in a thickness direction, and a photoelectric conversion cell provided in the semiconductor layer and partitioned by a first isolation region. The photoelectric conversion cell includes a first photoelectric conversion region adjacent to a second photoelectric conversion region in plan view and each having a photoelectric conversion unit and a transfer transistor, a second isolation region arranged between the first photoelectric conversion region and the second photoelectric conversion region in plan view and extending in a thickness direction of the semiconductor layer, and an element formation region partitioned on the first surface side of the semiconductor layer by a third isolation region and provided with a pixel transistor. The element formation region extends over the first and second photoelectric conversion regions in plan view.
    Type: Application
    Filed: March 9, 2022
    Publication date: February 1, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hirofumi YAMASHITA, Chihiro TOMITA, Harumi TANAKA
  • Publication number: 20230420478
    Abstract: An imaging element according to an embodiment of the present disclosure includes: a first substrate, a second substrate, and a third substrate that are stacked in this order. The first substrate including a sensor pixel that performs photoelectric conversion and the second substrate including a readout circuit are electrically coupled to each other by a first through wiring line provided in an interlayer insulating film. The second substrate and the third substrate including a logic circuit are electrically coupled to each other by a junction between pad electrodes or a second through wiring line penetrating through a semiconductor substrate.
    Type: Application
    Filed: September 14, 2023
    Publication date: December 28, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Keiichi NAKAZAWA, Yoshiaki KITANO, Hirofumi YAMASHITA, Minoru ISHIDA
  • Patent number: 11798972
    Abstract: An imaging element according to an embodiment of the present disclosure includes: a first substrate, a second substrate, and a third substrate that are stacked in this order. The first substrate including a sensor pixel that performs photoelectric conversion and the second substrate including a readout circuit are electrically coupled to each other by a first through wiring line provided in an interlayer insulating film. The second substrate and the third substrate including a logic circuit are electrically coupled to each other by a junction between pad electrodes or a second through wiring line penetrating through a semiconductor substrate.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: October 24, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Keiichi Nakazawa, Yoshiaki Kitano, Hirofumi Yamashita, Minoru Ishida