Patents by Inventor Hirofumi Yamashita
Hirofumi Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240121529Abstract: To provide a solid-state imaging device and an electronic apparatus capable of achieving both of a high dynamic range operation and an auto focus operation in a pixel configuration in which a plurality of unit pixels includes two or more subpixels. There is provided a solid-state imaging device including: a first pixel separation region that separates a plurality of unit pixels including two or more subpixels; a second pixel separation region that separates each of the plurality of unit pixels separated by the first pixel separation region; and an overflow region that causes signal charges accumulated in the subpixels to overflow to at least one of adjacent subpixels, in which the overflow region is formed between a first subpixel and a second subpixel.Type: ApplicationFiled: December 19, 2023Publication date: April 11, 2024Inventors: HIROFUMI YAMASHITA, SHOHEI SHIMADA, YUSUKE OTAKE, YUSUKE TANAKA, TOSHIFUMI WAKANO
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Patent number: 11948963Abstract: Provided is an imaging apparatus including an imaging unit having a plurality of pixels, the pixels each having: a conversion element converting incident light into photoelectrons; a floating diffusion layer electrically connected to the conversion element and converting the photoelectrons into a voltage signal; a differential amplifier circuit electrically connected to the floating diffusion layer, including an amplifier transistor to which a potential of the floating diffusion layer is input, and amplifying the potential of the floating diffusion layer; a feedback transistor electrically connected to the amplifier transistor and initializing the differential amplifier circuit; a clamp capacitance connected in series between the floating diffusion layer and the amplifier transistor; and a reset transistor connected in parallel between the floating diffusion layer and the clamp capacitance and initializing the potential of the floating diffusion layer.Type: GrantFiled: February 27, 2023Date of Patent: April 2, 2024Assignee: Sony Semiconductor Solutions CorporationInventor: Hirofumi Yamashita
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Patent number: 11937002Abstract: Provided is a solid-state imaging device and an electronic apparatus capable of achieving both of a high dynamic range operation and an auto focus operation in a pixel configuration in which a plurality of unit pixels includes two or more subpixels. The solid-state imaging device includes a first pixel separation region that separates a plurality of unit pixels including two or more subpixels, a second pixel separation region that separates each of the plurality of unit pixels separated by the first pixel separation region and an overflow region that causes signal charges accumulated in the subpixels to overflow to at least one of adjacent subpixels, in which the overflow region is formed between a first subpixel and a second subpixel.Type: GrantFiled: November 8, 2022Date of Patent: March 19, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hirofumi Yamashita, Shohei Shimada, Yusuke Otake, Yusuke Tanaka, Toshifumi Wakano
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Patent number: 11890298Abstract: To develop a novel administration method of a fucoidan-containing hair-growing agent and to provide a means for exerting excellent effects of a fucoidan. A hair-growing agent of the present invention is characterized in that it is composed of a combination of a fucoidan-containing microneedle and a fucoidan-containing liniment. A base of the fucoidan-containing microneedle is preferably a biosoluble polymer. A hair-growing method of the present invention is characterized in that the fucoidan-containing microneedle and the fucoidan-containing liniment are concomitantly used.Type: GrantFiled: October 11, 2021Date of Patent: February 6, 2024Assignee: COSMED PHARMACEUTICAL CO., LTD.Inventors: Ying-shu Quan, Hirofumi Yamashita, Fumio Kamiyama, Akira Yamamoto, Hidemasa Katsumi
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Patent number: 11893394Abstract: Systems, methods, and other embodiments described herein relate to validating programs of a computing system in a vehicle by tracking a boot sequence. In one embodiment, a method includes, responsive to detecting initiation of a boot sequence in a computing system, tracking characteristics of programs executing as part of the boot sequence. The method includes determining whether the programs correspond with a program execution graph (PEG) by comparing the characteristics of the programs as the programs boot with the PEG. The method includes providing a response to thwart a malicious program when the boot sequence does not match the PEG.Type: GrantFiled: April 5, 2022Date of Patent: February 6, 2024Assignee: DENSO CORPORATIONInventors: Carlos Mora-Golding, Ameer Kashani, Gopalakrishnan Iyer, Hirofumi Yamashita
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Publication number: 20240038815Abstract: A light detecting device includes a semiconductor layer having a first surface and a second surface located on opposite sides to each other in a thickness direction, and a photoelectric conversion cell provided in the semiconductor layer and partitioned by a first isolation region. The photoelectric conversion cell includes a first photoelectric conversion region adjacent to a second photoelectric conversion region in plan view and each having a photoelectric conversion unit and a transfer transistor, a second isolation region arranged between the first photoelectric conversion region and the second photoelectric conversion region in plan view and extending in a thickness direction of the semiconductor layer, and an element formation region partitioned on the first surface side of the semiconductor layer by a third isolation region and provided with a pixel transistor. The element formation region extends over the first and second photoelectric conversion regions in plan view.Type: ApplicationFiled: March 9, 2022Publication date: February 1, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hirofumi YAMASHITA, Chihiro TOMITA, Harumi TANAKA
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Publication number: 20230420478Abstract: An imaging element according to an embodiment of the present disclosure includes: a first substrate, a second substrate, and a third substrate that are stacked in this order. The first substrate including a sensor pixel that performs photoelectric conversion and the second substrate including a readout circuit are electrically coupled to each other by a first through wiring line provided in an interlayer insulating film. The second substrate and the third substrate including a logic circuit are electrically coupled to each other by a junction between pad electrodes or a second through wiring line penetrating through a semiconductor substrate.Type: ApplicationFiled: September 14, 2023Publication date: December 28, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Keiichi NAKAZAWA, Yoshiaki KITANO, Hirofumi YAMASHITA, Minoru ISHIDA
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Patent number: 11798972Abstract: An imaging element according to an embodiment of the present disclosure includes: a first substrate, a second substrate, and a third substrate that are stacked in this order. The first substrate including a sensor pixel that performs photoelectric conversion and the second substrate including a readout circuit are electrically coupled to each other by a first through wiring line provided in an interlayer insulating film. The second substrate and the third substrate including a logic circuit are electrically coupled to each other by a junction between pad electrodes or a second through wiring line penetrating through a semiconductor substrate.Type: GrantFiled: December 12, 2022Date of Patent: October 24, 2023Assignee: Sony Semiconductor Solutions CorporationInventors: Keiichi Nakazawa, Yoshiaki Kitano, Hirofumi Yamashita, Minoru Ishida
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Publication number: 20230315484Abstract: Systems, methods, and other embodiments described herein relate to validating programs of a computing system in a vehicle by tracking a boot sequence. In one embodiment, a method includes, responsive to detecting initiation of a boot sequence in a computing system, tracking characteristics of programs executing as part of the boot sequence. The method includes determining whether the programs correspond with a program execution graph (PEG) by comparing the characteristics of the programs as the programs boot with the PEG. The method includes providing a response to thwart a malicious program when the boot sequence does not match the PEG.Type: ApplicationFiled: April 5, 2022Publication date: October 5, 2023Inventors: Carlos Mora-Golding, Ameer Kashani, Gopalakrishnan Iyer, Hirofumi Yamashita
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Publication number: 20230306110Abstract: Systems, methods, and other embodiments described herein relate to adaptable canary values. In one embodiment, a method includes acquiring state information about a program executing within a vehicle. The state information specifies at least a security level of segments of the program. The method includes, responsive to the program satisfying a generating threshold, generating a canary value according to the state information. The method includes inserting the canary value into a memory address associated with the program.Type: ApplicationFiled: March 8, 2022Publication date: September 28, 2023Inventors: Ameer Kashani, Gopalakrishnan Iyer, Carlos Mora-Golding, Hirofumi Yamashita
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Publication number: 20230289435Abstract: Systems, methods, and other embodiments described herein relate to improving incident response within a vehicle environment. In one embodiment, a method includes, responsive to detecting an attack on a threatened component of a computing system, gathering information about the threatened component, including at least a dependency list that specifies related components to the threatened component. The method includes determining a risk score for the attack according to a risk level associated with the attack, a risk type of the threatened component, and combined risks associated with compromising the related components. The method includes providing a report specifying information about the attack, including at least the risk score.Type: ApplicationFiled: March 10, 2022Publication date: September 14, 2023Inventors: Carlos Mora-Golding, Ameer Kashani, Gopalakrishnan Iyer, Hirofumi Yamashita
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Publication number: 20230290802Abstract: Provided is an imaging apparatus including an imaging unit having a plurality of pixels, the pixels each having: a conversion element converting incident light into photoelectrons; a floating diffusion layer electrically connected to the conversion element and converting the photoelectrons into a voltage signal; a differential amplifier circuit electrically connected to the floating diffusion layer, including an amplifier transistor to which a potential of the floating diffusion layer is input, and amplifying the potential of the floating diffusion layer; a feedback transistor electrically connected to the amplifier transistor and initializing the differential amplifier circuit; a clamp capacitance connected in series between the floating diffusion layer and the amplifier transistor; and a reset transistor connected in parallel between the floating diffusion layer and the clamp capacitance and initializing the potential of the floating diffusion layer.Type: ApplicationFiled: February 27, 2023Publication date: September 14, 2023Inventor: Hirofumi Yamashita
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Publication number: 20230233823Abstract: Provided is a micro-needle array in which all fine needles can be more easily inserted into the skin regardless of positions where the fine needles of the micro-needle array are located on a substrate. The micro-needle array includes: a substrate; and a plurality of micro-needles arranged on one surface of the substrate. Tip parts of the plurality of micro-needles have a height difference, and the micro-needles have a needle length of 80 ?m or more and 2000 ?m or less. The height difference of the plurality of micro-needles is preferably based on unevenness of the substrate.Type: ApplicationFiled: May 24, 2021Publication date: July 27, 2023Inventors: Ying-shu Quan, Ying-zhe Li, Kenji Kajiyama, Mio Saito, Hirofumi Yamashita, Fumio Kamiyama
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Publication number: 20230154964Abstract: An imaging element according to an embodiment of the present disclosure includes: a first substrate, a second substrate, and a third substrate that are stacked in this order. The first substrate including a sensor pixel that performs photoelectric conversion and the second substrate including a readout circuit are electrically coupled to each other by a first through wiring line provided in an interlayer insulating film. The second substrate and the third substrate including a logic circuit are electrically coupled to each other by a junction between pad electrodes or a second through wiring line penetrating through a semiconductor substrate.Type: ApplicationFiled: December 12, 2022Publication date: May 18, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Keiichi NAKAZAWA, Yoshiaki KITANO, Hirofumi YAMASHITA, Minoru ISHIDA
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Patent number: 11610931Abstract: Provided is an imaging apparatus including an imaging unit having a plurality of pixels, the pixels each having: a conversion element converting incident light into photoelectrons; a floating diffusion layer electrically connected to the conversion element and converting the photoelectrons into a voltage signal; a differential amplifier circuit electrically connected to the floating diffusion layer, including an amplifier transistor to which a potential of the floating diffusion layer is input, and amplifying the potential of the floating diffusion layer; a feedback transistor electrically connected to the amplifier transistor and initializing the differential amplifier circuit; a clamp capacitance connected in series between the floating diffusion layer and the amplifier transistor; and a reset transistor connected in parallel between the floating diffusion layer and the clamp capacitance and initializing the potential of the floating diffusion layer.Type: GrantFiled: February 17, 2022Date of Patent: March 21, 2023Assignee: Sony Semiconductor Solutions CorporationInventor: Hirofumi Yamashita
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Patent number: 11600651Abstract: An imaging element according to an embodiment of the present disclosure includes: a first substrate, a second substrate, and a third substrate that are stacked in this order. The first substrate including a sensor pixel that performs photoelectric conversion and the second substrate including a readout circuit are electrically coupled to each other by a first through wiring line provided in an interlayer insulating film. The second substrate and the third substrate including a logic circuit are electrically coupled to each other by a junction between pad electrodes or a second through wiring line penetrating through a semiconductor substrate.Type: GrantFiled: December 27, 2018Date of Patent: March 7, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Keiichi Nakazawa, Yoshiaki Kitano, Hirofumi Yamashita, Minoru Ishida
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Publication number: 20230067160Abstract: To provide a solid-state imaging device and an electronic apparatus capable of achieving both of a high dynamic range operation and an auto focus operation in a pixel configuration in which a plurality of unit pixels includes two or more subpixels. There is provided a solid-state imaging device including: a first pixel separation region that separates a plurality of unit pixels including two or more subpixels; a second pixel separation region that separates each of the plurality of unit pixels separated by the first pixel separation region; and an overflow region that causes signal charges accumulated in the subpixels to overflow to at least one of adjacent subpixels, in which the overflow region is formed between a first subpixel and a second subpixel.Type: ApplicationFiled: November 8, 2022Publication date: March 2, 2023Inventors: HIROFUMI YAMASHITA, SHOHEI SHIMADA, YUSUKE OTAKE, YUSUKE TANAKA, TOSHIFUMI WAKANO
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Patent number: 11569279Abstract: There is provided a solid-state imaging device that includes a photoelectric conversion unit, a transfer gate, a floating diffusion unit, and a transistor. The photoelectric conversion unit produces a charge according to incident light. The transfer gate has a columnar shape having an opening that is continuous in a vertical direction, and transfers the charge from the photoelectric conversion unit. The floating diffusion unit is formed extending to a region surrounded by the opening of the transfer gate, and converts the transferred charge into a voltage signal. The transistor is electrically connected to the floating diffusion unit via a diffusion layer.Type: GrantFiled: September 14, 2018Date of Patent: January 31, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hironobu Fukui, Hirofumi Yamashita
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Patent number: 11523078Abstract: Provided is a solid-state imaging device and an electronic apparatus capable of achieving both of a high dynamic range operation and an auto focus operation in a pixel configuration in which a plurality of unit pixels includes two or more subpixels. The solid-state imaging device includes a first pixel separation region that separates a plurality of unit pixels including two or more subpixels, a second pixel separation region that separates each of the plurality of unit pixels separated by the first pixel separation region and an overflow region that causes signal charges accumulated in the subpixels to overflow to at least one of adjacent subpixels, in which the overflow region is formed between a first subpixel and a second subpixel.Type: GrantFiled: July 8, 2019Date of Patent: December 6, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hirofumi Yamashita, Shohei Shimada, Yusuke Otake, Yusuke Tanaka, Toshifumi Wakano
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Publication number: 20220359602Abstract: A second substrate including a pixel circuit that outputs a pixel signal on a basis of electric charges outputted from the sensor pixel and a third substrate including a processing circuit that performs signal processing on the pixel signal are provided. The first substrate, the second substrate, and the third substrate are stacked in this order. A semiconductor layer including the pixel circuit is divided by an insulating layer. The insulating layer divides the semiconductor layer to allow a center position of a continuous region of the semiconductor layer or a center position of a region that divides the semiconductor layer to correspond to a position of an optical center of the sensor pixel, in at least one direction on a plane of the sensor pixel perpendicular to an optical axis direction.Type: ApplicationFiled: June 23, 2020Publication date: November 10, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Hirofumi YAMASHITA