Patents by Inventor Hirohiko Nishiki

Hirohiko Nishiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10690975
    Abstract: Provided are an active-matrix substrate, a method for manufacturing the same, and a display device, which render it possible to inhibit electrostatic discharge from occurring during the process of manufacturing a display panel and suppress manufacturing cost. An IGZO film, which is positioned between a silicon oxide film included in a gate insulating film and an etch-stop layer, is annealed at 200 to 350° C. after a passivation film for protecting a TFT is formed. As a result, the passivation film is annealed, and the IGZO film is changed from a conductor to a semiconductor. Consequently, it is not only possible to suppress the occurrence of ESD, but also possible to eliminate the need to sever an electrostatic discharge prevention circuit from a display panel, resulting in a reduced cost of manufacturing a display device.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: June 23, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Shinji Nakajima, Izumi Ishida, Shogo Murashige
  • Publication number: 20200194254
    Abstract: Provided is a method for manufacturing a semiconductor device, the semiconductor device including a substrate, and an oxide semiconductor TFT that is supported by the substrate and includes an oxide semiconductor film as an active layer. The method includes: (A) preparing MO gas containing a first organometallic compound that contains In and a second organometallic compound that contains Zn; and (B) supplying gas containing the MO gas and oxygen to the substrate placed in a chamber under a condition in which the substrate is heated to 500° C. or lower, and growing an oxide semiconductor film containing In and Zn on the substrate using an MOCVD method. Step (B) is performed under a condition in which plasma is formed in the chamber.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 18, 2020
    Inventors: Shinji NAKAJIMA, Hirohiko NISHIKI, Hirohide MIMURA, Yuhichi SAITOH, Yujiro TAKEDA, Shogo MURASHIGE, Izumi ISHIDA, Tohru OKABE
  • Patent number: 10685598
    Abstract: A wiring delay is prevented or reduced by lowering a wiring resistance without making a wire wider. The present invention includes: a light blocking film (102); a light-transmitting film (106); and a first wiring layer (105A) which serves as part of a wire configured to electrically control an amount of transmitted light for each pixel, the first wiring layer (105A) being provided over the light blocking film (102), and the light-transmitting film (106) being provided over the first wiring layer (105A) so as to cover a side surface of the first wiring layer.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: June 16, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Shinji Nakajima, Izumi Ishida, Shogo Murashige
  • Patent number: 10670933
    Abstract: Provided are an active-matrix substrate having a reliable line connection structure, a method for producing the same, and a display device including the same. A first metal line 122 and a second metal line 125 are electrically connected via an IGZO layer 124 rendered conductive. In this case, the second metal line 125 is isolated from an ITO layer 109 without contacting the ITO layer 109 because there are a passivation layer 107 and an organic insulating film 108 formed between the second metal line 125 and the ITO layer 109. Thus, no contact fault due to electric corrosion occurs between an aluminum layer 125a of the second metal line 125 and the ITO layer 109, whereby a reliable line connection structure is achieved.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: June 2, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Yaneda
  • Patent number: 10529743
    Abstract: Disclosed is an active matrix substrate that includes a plurality of TFTs. The active matrix substrate 11 includes a substrate 100, TFTs, a light transmission film 204, and a protection film Cap4. The TFTs are provided on the substrate 100 so as to correspond to a plurality of pixels, respectively. The light transmission film 204 is provided between the TFTs and the substrate 100. The protection film Cap4 covers an end surface 204b of the light transmission film 204, the end surface 204b being not parallel with the substrate 100. The TFT includes a gate electrode, a gate insulating film, a semiconductor film, a drain electrode, and a source electrode. The protection film Cap4 is arranged between the light transmission film 204 and the semiconductor film of the TFT.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: January 7, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shogo Murashige, Izumi Ishida, Tomohiro Kosaka, Tohru Okabe, Takeshi Hara, Hirohiko Nishiki
  • Publication number: 20190131322
    Abstract: A method for manufacturing a thin-film transistor that includes a source electrode and a drain electrode at least one of which has a layered structure of a plurality of metal layers including an Al layer and at least one layer made of a metal other than Al and a channel layer made of an oxide semiconductor includes forming a conductive film for the source electrode and the drain electrode, patterning the conductive film to form the source electrode and the drain electrode, forming a passivation film, and conducting heat treatment. The method includes preliminary heat treatment prior to the heat treatment, the preliminary heat treatment being conducted between the patterning of the conductive film and the formation of the passivation film.
    Type: Application
    Filed: October 26, 2018
    Publication date: May 2, 2019
    Inventors: Kazuatsu ITO, Hirohiko NISHIKI
  • Publication number: 20190129267
    Abstract: Provided are an active-matrix substrate having a reliable line connection structure, a method for producing the same, and a display device including the same. A first metal line 122 and a second metal line 125 are electrically connected via an IGZO layer 124 rendered conductive. In this case, the second metal line 125 is isolated from an ITO layer 109 without contacting the ITO layer 109 because there are a passivation layer 107 and an organic insulating film 108 formed between the second metal line 125 and the ITO layer 109. Thus, no contact fault due to electric corrosion occurs between an aluminum layer 125a of the second metal line 125 and the ITO layer 109, whereby a reliable line connection structure is achieved.
    Type: Application
    Filed: May 2, 2017
    Publication date: May 2, 2019
    Inventors: Tohru OKABE, Hirohiko NISHIKI, Takeshi YANEDA
  • Publication number: 20190123119
    Abstract: An organic EL display apparatus includes a substrate, and a pixel circuit provided for each pixel. The pixel circuit includes a first oxide semiconductor TFT having a first oxide semiconductor layer, and a second oxide semiconductor TFT having a second oxide semiconductor layer. The first oxide semiconductor TFT has a top-gate structure. The second oxide semiconductor TFT has a bottom-gate structure. The second oxide semiconductor TFT has a shield electrode that is disposed on an insulating layer disposed on the second oxide semiconductor layer, facing the second oxide semiconductor layer.
    Type: Application
    Filed: October 18, 2018
    Publication date: April 25, 2019
    Inventors: Tadayoshi MIYAMOTO, Mari HOSOKAWA, Yoshinobu NAKAMURA, Hirohiko NISHIKI
  • Publication number: 20190113813
    Abstract: Provided are an active-matrix substrate, a method for manufacturing the same, and a display device, which render it possible to inhibit electrostatic discharge from occurring during the process of manufacturing a display panel and suppress manufacturing cost. An IGZO film, which is positioned between a silicon oxide film included in a gate insulating film and an etch-stop layer, is annealed at 200 to 350° C. after a passivation film for protecting a TFT is formed. As a result, the passivation film is annealed, and the IGZO film is changed from a conductor to a semiconductor. Consequently, it is not only possible to suppress the occurrence of ESD, but also possible to eliminate the need to sever an electrostatic discharge prevention circuit from a display panel, resulting in a reduced cost of manufacturing a display device.
    Type: Application
    Filed: March 24, 2017
    Publication date: April 18, 2019
    Inventors: Tohru OKABE, Hirohiko NISHIKI, Shinji NAKAJIMA, Izumi ISHIDA, Shogo MURASHIGE
  • Publication number: 20190103052
    Abstract: A wiring delay is prevented or reduced by lowering a wiring resistance without making a wire wider. The present invention includes: a light blocking film (102); a light-transmitting film (106); and a first wiring layer (105A) which serves as part of a wire configured to electrically control an amount of transmitted light for each pixel, the first wiring layer (105A) being provided over the light blocking film (102), and the light-transmitting film (106) being provided over the first wiring layer (105A) so as to cover a side surface of the first wiring layer.
    Type: Application
    Filed: March 27, 2017
    Publication date: April 4, 2019
    Inventors: Tohru OKABE, Hirohiko NISHIKI, Shinji NAKAJIMA, Izumi ISHIDA, Shogo MURASHIGE
  • Publication number: 20190081081
    Abstract: Disclosed is an active matrix substrate that includes a plurality of TFTs. The active matrix substrate 11 includes a substrate 100, TFTs, a light transmission film 204, and a protection film Cap4. The TFTs are provided on the substrate 100 so as to correspond to a plurality of pixels, respectively. The light transmission film 204 is provided between the TFTs and the substrate 100. The protection film Cap4 covers an end surface 204b of the light transmission film 204, the end surface 204b being not parallel with the substrate 100. The TFT includes a gate electrode, a gate insulating film, a semiconductor film, a drain electrode, and a source electrode. The protection film Cap4 is arranged between the light transmission film 204 and the semiconductor film of the TFT.
    Type: Application
    Filed: July 7, 2016
    Publication date: March 14, 2019
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: SHOGO MURASHIGE, IZUMI ISHIDA, TOMOHIRO KOSAKA, TOHRU OKABE, TAKESHI HARA, HIROHIKO NISHIKI
  • Patent number: 10209592
    Abstract: An active matrix substrate includes an insulating substrate in which light-transmitting areas and a light-shielding area are formed. The active matrix substrate further includes: a light-shielding film formed in the light-shielding area on the insulating substrate, with a transparent base material containing carbon particles, the light shielding film being colored with the carbon particles; an inorganic film formed on the light-shielding film; light-transmitting films formed in the light-transmitting areas on the insulating substrate, with a transparent base material containing transparent oxidized carbon particles; gate lines provided on the inorganic film; a gate insulating film provided on the gate lines; thin film transistors provided in matrix on the gate insulating film; and data lines provided on the light-shielding film to intersect with the gate lines. The data lines are electrically connected with the thin film transistors.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: February 19, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Hara, Tomohiro Kosaka, Izumi Ishida, Shogo Murashige
  • Publication number: 20180254293
    Abstract: An active matrix substrate 10 includes: an insulating substrate 110; a first conductive film 130 formed on the insulating substrate 110; a light-transmitting film 114 formed on the insulating substrate 110 so that the light-transmitting film 114 covers the first conductive film 130; a second conductive film 140 formed on the light-transmitting film 114; a first insulating layer 115 formed on the light-transmitting film 114 so that the first insulating layer 115 covers the second conductive film 140; a semiconductor film 170 formed on the first insulating layer 115; and a third conductive film 150 formed on the first insulating layer 115 and the semiconductor film 170. The first conductive film 130 and the second conductive film 140 are electrically connected via the third conductive film 150.
    Type: Application
    Filed: September 7, 2016
    Publication date: September 6, 2018
    Inventors: TOHRU OKABE, HIROHIKO NISHIKI, TAKESHI HARA, TOMOHIRO KOSAKA, IZUMI ISHIDA, SHOGO MURASHIGE
  • Publication number: 20180239127
    Abstract: A display device includes: a translucent substrate; a light-shielding film provided on the translucent substrate; first transparent insulating films that are provided on the translucent substrate so as to cover the covering the light-blocking film; and a plurality of thin film transistors (TFTs) that are provided on the first transparent insulation films and include a portion of lines made of conductive films. The light-shielding film is arranged so as to overlap at least the TFTs, when viewed in a direction vertical to the translucent substrate.
    Type: Application
    Filed: August 31, 2015
    Publication date: August 23, 2018
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Hirohiko NISHIKI, Tohru OKABE
  • Publication number: 20180210306
    Abstract: An active matrix substrate includes an insulating substrate 100 in which light-transmitting areas and a light-shielding area are formed. The active matrix substrate further includes: a light-shielding film 201 formed in the light-shielding area on the insulating substrate 100, with a transparent base material containing carbon particles, the light shielding film being colored with the carbon particles; an inorganic film 202 formed on the light-shielding film; light-transmitting films 204 formed in the light-transmitting areas on the insulating substrate, with a transparent base material containing transparent oxidized carbon particles; gate lines 111 provided on the inorganic film; a gate insulating film 101 provided on the gate lines; thin film transistors 300 provided in matrix on the gate insulating film; and data lines provided on the light-shielding film to intersect with the gate lines. The data lines are electrically connected with the thin film transistors 300.
    Type: Application
    Filed: July 7, 2016
    Publication date: July 26, 2018
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: TOHRU OKABE, HIROHIKO NISHIKI, TAKESHI HARA, TOMOHIRO KOSAKA, IZUMI ISHIDA, SHOGO MURASHIGE
  • Publication number: 20180188575
    Abstract: An active matrix substrate includes an insulating substrate (100); a surface coating film (110) that covers at least a part of a surface of the insulating substrate; an insulating light-transmitting film (204) provided on the insulating substrate including the surface coating film; gate lines; a gate insulating film; thin film transistors; data lines; and lead-out lines (115). In a peripheral portion of the insulating substrate, an area where the insulating light-transmitting film is not provided is formed. The lead-out line is provided so as to intersect with an outer circumference end of the insulating light-transmitting film, when viewed in a direction vertical to the insulating substrate. In the area where the insulating light-transmitting film is not provided, the surface coating film is also provided on a part in contact with the outer circumference end of the insulating light-transmitting film.
    Type: Application
    Filed: July 7, 2016
    Publication date: July 5, 2018
    Inventors: TOMOHIRO KOSAKA, TAKESHI HARA, TOHRU OKABE, IZUMI ISHIDA, SHOGO MURASHIGE, KENICHI KITOH, HIROHIKO NISHIKI
  • Patent number: 9853164
    Abstract: This semiconductor device is provided with: a semiconductor film that comprises an oxide semiconductor, and includes a channel region; a first inorganic insulating film formed on the semiconductor film; a first organic insulating film formed on the first inorganic insulating film; and an inorganic film group. The inorganic film group has: a first electrode comprising an inorganic conductive film formed on the first organic insulating film; a second inorganic insulating film formed on the first electrode; and a second electrode that comprises an inorganic conductive film formed on the second inorganic insulating film, and is electrically connected to the semiconductor film via openings formed in such a manner as to penetrate the first inorganic insulating film, the first organic insulating film, the first electrode and the second inorganic insulating film. The first organic insulating film is disposed between the first inorganic insulating film and the inorganic film group.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: December 26, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takeshi Hara, Hirohiko Nishiki, Izumi Ishida, Shogo Murashige
  • Patent number: 9716183
    Abstract: A semiconductor device includes a thin film transistor (100), the thin film transistor (100) including: a substrate (1); a gate electrode (3) provided on the substrate (1); a gate dielectric layer (5) formed on the gate electrode (3); an island-shaped oxide semiconductor layer (7) formed on the gate dielectric layer (5); a protective layer (9) provided so as to cover an upper face (7u) and an entire side face (7e) of the oxide semiconductor layer (7), the protective layer (9) having a single opening (9p) through which the upper face (7u) of the oxide semiconductor layer (7) is only partially exposed; and a source electrode (11) and a drain electrode (13) which are in contact with the oxide semiconductor layer (7) within the single opening (9p).
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: July 25, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hirohiko Nishiki, Akira Sasakura, Tohru Okabe
  • Publication number: 20170018646
    Abstract: A semiconductor device includes a thin film transistor (100), the thin film transistor (100) including: a substrate (1); a gate electrode (3) provided on the substrate (1); a gate dielectric layer (5) formed on the gate electrode (3); an island-shaped oxide semiconductor layer (7) formed on the gate dielectric layer (5); a protective layer (9) provided so as to cover an upper face (7u) and an entire side face (7e) of the oxide semiconductor layer (7), the protective layer (9) having a single opening (9p) through which the upper face (7u) of the oxide semiconductor layer (7) is only partially exposed; and a source electrode (11) and a drain electrode (13) which are in contact with the oxide semiconductor layer (7) within the single opening (9p).
    Type: Application
    Filed: March 10, 2015
    Publication date: January 19, 2017
    Inventors: Hirohiko NISHIKI, Akira SASAKURA, Tohru OKABE
  • Patent number: 9519198
    Abstract: A liquid crystal display device, which includes: a liquid crystal layer; and a first substrate and a second substrate that are arranged so as to face each other with the liquid crystal layer being sandwiched therebetween. On the liquid crystal layer side of the first substrate, there are provided: a plurality of first thin film transistors that are arranged in a display region; a peripheral drive circuit which includes a plurality of second thin film transistors and is arranged in the periphery of the display region so as to supply drive signals to the plurality of first thin film transistors; an organic insulating film that is formed so as to cover the plurality of first thin film transistors and the plurality of second thin film transistors; and an inorganic insulating film that is formed on the organic insulating film.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: December 13, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hirohiko Nishiki, Takeshi Hara, Tohru Okabe