Patents by Inventor Hirohiko Nishiki

Hirohiko Nishiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11107845
    Abstract: A Thin Film Transistor (TFT) substrate includes a first semiconductor film, a first electrically conductive member provided in a layer higher than the first semiconductor film, an interlayer insulating film provided in a layer higher than the first electrically conductive member and including a first through hole, a second semiconductor film provided in a layer higher than the interlayer insulating film, a second electrically conductive member provided in a layer higher than the second semiconductor film, an organic insulating film provided in a layer higher than the second electrically conductive member and including a second through hole, and a third electrically conductive member provided in a layer higher than the organic insulating film. A contact hole extends through the first and the second through hole to the first electrically conductive member.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: August 31, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Yaneda
  • Patent number: 11043600
    Abstract: A semiconductor device includes a substrate and an oxide semiconductor TFT supported by the substrate. The oxide semiconductor TFT includes an oxide semiconductor layer containing In, Ga, and Zn, a gate electrode, a gate insulating layer formed between the gate electrode and the oxide semiconductor layer, and a source electrode and a drain electrode that are in contact with the oxide semiconductor layer. The oxide semiconductor layer has a layered structure that includes a first layer, a second layer, and an intermediate transition layer disposed between the first layer and the second layer, and the first layer is disposed closer to the gate insulating layer side than the second layer. The first layer and the second layer have different compositions, and the intermediate transition layer has a continuously changing composition from the first layer side toward the second layer side.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: June 22, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shinji Nakajima, Hirohiko Nishiki, Yujiro Takeda, Shogo Murashige
  • Patent number: 11028270
    Abstract: [Problem] To provide a composition for a black matrix which is a material suitable for manufacturing a black matrix, which is suitable for a high luminance display device structure and has high heat resistance and high light-shielding properties. [Means for Solution] The present invention uses a composition for a black matrix comprising: (I) a black colorant containing carbon black having a volume average particle diameter of 1 to 300 nm; (II) a siloxane polymer to be obtained by hydrolyzing and condensing a silane compound represented by a prescribed formula in the presence of an acidic or basic catalyst; (III) surface modified silica fine particles; (IV) a thermal base generator; and (V) a solvent.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: June 8, 2021
    Assignee: Merck Patent GmbH
    Inventors: Hirohiko Nishiki, Tohru Okabe, Izumi Ishida, Shogo Murashige, Atsuko Noya, Toshiaki Nonaka, Naofumi Yoshida
  • Patent number: 11024656
    Abstract: An active matrix substrate in which step-caused disconnection of a metal film in a contact hole does not easily occur includes a first to third insulating films and first to third metal films on a glass substrate and a contact hole electrically connecting the first and second metal film, the contact hole including first to third hole present respectively in the first to third insulating films, the first and third metal films being in contact with each other inside the first hole, the second insulating film and an oxide semiconductor film overlapping with each other in a region below the third hole, the second and third metal films being in contact with each other in a region above the first insulating film and either inside or below the third hole.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: June 1, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Yaneda
  • Publication number: 20210135013
    Abstract: A semiconductor device includes a substrate and an oxide semiconductor TFT supported by the substrate. The oxide semiconductor TFT includes an oxide semiconductor layer containing In, Ga, and Zn, a gate electrode, a gate insulating layer formed between the gate electrode and the oxide semiconductor layer, and a source electrode and a drain electrode that are in contact with the oxide semiconductor layer. The oxide semiconductor layer has a layered structure that includes a first layer, a second layer, and an intermediate transition layer disposed between the first layer and the second layer, and the first layer is disposed closer to the gate insulating layer side than the second layer. The first layer and the second layer have different compositions, and the intermediate transition layer has a continuously changing composition from the first layer side toward the second layer side.
    Type: Application
    Filed: December 15, 2017
    Publication date: May 6, 2021
    Inventors: Shinji NAKAJIMA, Hirohiko NISHIKI, Yujiro TAKEDA, Shogo MURASHIGE
  • Patent number: 10991729
    Abstract: An active matrix substrate having low susceptibility to contact failure between two conductor films is provided. An oxide semiconductor film converted into a conductor is provided in a layer between a substrate and a first metal film. Within a contact hole, the oxide semiconductor film converted into a conductor is in contact with a second metal film. Outside of the contact hole, the oxide semiconductor film converted into a conductor is in contact with the first metal film.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: April 27, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Yaneda
  • Publication number: 20210020662
    Abstract: A display device includes an active matrix substrate, wherein the active matrix substrate is layered with a base insulating film, a first metal layer, a metal oxide layer, a first inorganic insulating film, an oxide semiconductor layer, a second inorganic insulating film, a second metal layer, an interlayer insulating layer, and a third metal layer in order from a lower layer, and the active matrix substrate includes a first transistor configured of a first bottom gate electrode, a top gate electrode, and a source electrode and a drain electrode formed by the third metal layer, the source electrode and the drain electrode are respectively electrically connected to a source region and a drain region of the oxide semiconductor layer, the first bottom gate electrode is superimposed over the oxide semiconductor layer, and a metal of the first metal layer is different from a metal of the metal oxide layer.
    Type: Application
    Filed: March 30, 2018
    Publication date: January 21, 2021
    Inventors: IZUMI ISHIDA, HIROHIKO NISHIKI, YUJIRO TAKEDA
  • Patent number: 10879064
    Abstract: Provided is a method for manufacturing a semiconductor device, the semiconductor device including a substrate, and an oxide semiconductor TFT that is supported by the substrate and includes an oxide semiconductor film as an active layer. The method includes: (A) preparing MO gas containing a first organometallic compound that contains In and a second organometallic compound that contains Zn; and (B) supplying gas containing the MO gas and oxygen to the substrate placed in a chamber under a condition in which the substrate is heated to 500° C. or lower, and growing an oxide semiconductor film containing In and Zn on the substrate using an MOCVD method. Step (B) is performed under a condition in which plasma is formed in the chamber.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 29, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shinji Nakajima, Hirohiko Nishiki, Hirohide Mimura, Yuhichi Saitoh, Yujiro Takeda, Shogo Murashige, Izumi Ishida, Tohru Okabe
  • Publication number: 20200381462
    Abstract: An embodiment of the present invention provides, in a TFT substrate having a lower layer portion and an upper layer portion each including a respective semiconductor film, a stable connection between an electrically conductive member of the lower layer portion and an electrically conductive member of the upper layer portion.
    Type: Application
    Filed: March 22, 2018
    Publication date: December 3, 2020
    Inventors: Tohru OKABE, Hirohiko NISHIKI, Takeshi YANEDA
  • Publication number: 20200328235
    Abstract: An active matrix substrate having low susceptibility to contact failure between two conductor films is provided. An oxide semiconductor film converted into a conductor is provided in a layer between a substrate and a first metal film. Within a contact hole, the oxide semiconductor film converted into a conductor is in contact with a second metal film. Outside of the contact hole, the oxide semiconductor film converted into a conductor is in contact with the first metal film.
    Type: Application
    Filed: June 16, 2017
    Publication date: October 15, 2020
    Inventors: Tohru OKABE, Hirohiko NISHIKI, Takeshi YANEDA
  • Publication number: 20200312888
    Abstract: An active matrix substrate in which step-caused disconnection of a metal film in a contact hole does not easily occur includes a first to third insulating films and first to third metal films on a glass substrate and a contact hole electrically connecting the first and second metal film, the contact hole including first to third hole present respectively in the first to third insulating films, the first and third metal films being in contact with each other inside the first hole, the second insulating film and an oxide semiconductor film overlapping with each other in a region below the third hole, the second and third metal films being in contact with each other in a region above the first insulating film and either inside or below the third hole.
    Type: Application
    Filed: June 21, 2017
    Publication date: October 1, 2020
    Inventors: Tohru OKABE, Hirohiko NISHIKI, Takeshi YANEDA
  • Publication number: 20200277494
    Abstract: [Problem] To provide a composition for a black matrix which is a material suitable for manufacturing a black matrix, which is suitable for a high luminance display device structure and has high heat resistance and high light-shielding properties. [Means for Solution] The present invention uses a composition for a black matrix comprising: (I) a black colorant containing carbon black having a volume average particle diameter of 1 to 300 nm; (II) a siloxane polymer to be obtained by hydrolyzing and condensing a silane compound represented by a prescribed formula in the presence of an acidic or basic catalyst; (III) surface modified silica fine particles; (IV) a thermal base generator; and (V) a solvent.
    Type: Application
    Filed: December 7, 2017
    Publication date: September 3, 2020
    Inventors: Hirohiko NISHIKI, TOHRU OKABE, IZUMI ISHIDA, SHOGO MURASHIGE, Atsuko NOYA, Toshiaki NONAKA, Naofumi YOSHIDA
  • Patent number: 10754146
    Abstract: A display device includes: a translucent substrate; a light-shielding film provided on the translucent substrate; first transparent insulating films that are provided on the translucent substrate so as to cover the covering the light-blocking film; and a plurality of thin film transistors (TFTs) that are provided on the first transparent insulation films and include a portion of lines made of conductive films. The light-shielding film is arranged so as to overlap at least the TFTs, when viewed in a direction vertical to the translucent substrate.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: August 25, 2020
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hirohiko Nishiki, Tohru Okabe
  • Patent number: 10690975
    Abstract: Provided are an active-matrix substrate, a method for manufacturing the same, and a display device, which render it possible to inhibit electrostatic discharge from occurring during the process of manufacturing a display panel and suppress manufacturing cost. An IGZO film, which is positioned between a silicon oxide film included in a gate insulating film and an etch-stop layer, is annealed at 200 to 350° C. after a passivation film for protecting a TFT is formed. As a result, the passivation film is annealed, and the IGZO film is changed from a conductor to a semiconductor. Consequently, it is not only possible to suppress the occurrence of ESD, but also possible to eliminate the need to sever an electrostatic discharge prevention circuit from a display panel, resulting in a reduced cost of manufacturing a display device.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: June 23, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Shinji Nakajima, Izumi Ishida, Shogo Murashige
  • Publication number: 20200194254
    Abstract: Provided is a method for manufacturing a semiconductor device, the semiconductor device including a substrate, and an oxide semiconductor TFT that is supported by the substrate and includes an oxide semiconductor film as an active layer. The method includes: (A) preparing MO gas containing a first organometallic compound that contains In and a second organometallic compound that contains Zn; and (B) supplying gas containing the MO gas and oxygen to the substrate placed in a chamber under a condition in which the substrate is heated to 500° C. or lower, and growing an oxide semiconductor film containing In and Zn on the substrate using an MOCVD method. Step (B) is performed under a condition in which plasma is formed in the chamber.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 18, 2020
    Inventors: Shinji NAKAJIMA, Hirohiko NISHIKI, Hirohide MIMURA, Yuhichi SAITOH, Yujiro TAKEDA, Shogo MURASHIGE, Izumi ISHIDA, Tohru OKABE
  • Patent number: 10685598
    Abstract: A wiring delay is prevented or reduced by lowering a wiring resistance without making a wire wider. The present invention includes: a light blocking film (102); a light-transmitting film (106); and a first wiring layer (105A) which serves as part of a wire configured to electrically control an amount of transmitted light for each pixel, the first wiring layer (105A) being provided over the light blocking film (102), and the light-transmitting film (106) being provided over the first wiring layer (105A) so as to cover a side surface of the first wiring layer.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: June 16, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Shinji Nakajima, Izumi Ishida, Shogo Murashige
  • Patent number: 10670933
    Abstract: Provided are an active-matrix substrate having a reliable line connection structure, a method for producing the same, and a display device including the same. A first metal line 122 and a second metal line 125 are electrically connected via an IGZO layer 124 rendered conductive. In this case, the second metal line 125 is isolated from an ITO layer 109 without contacting the ITO layer 109 because there are a passivation layer 107 and an organic insulating film 108 formed between the second metal line 125 and the ITO layer 109. Thus, no contact fault due to electric corrosion occurs between an aluminum layer 125a of the second metal line 125 and the ITO layer 109, whereby a reliable line connection structure is achieved.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: June 2, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Yaneda
  • Patent number: 10529743
    Abstract: Disclosed is an active matrix substrate that includes a plurality of TFTs. The active matrix substrate 11 includes a substrate 100, TFTs, a light transmission film 204, and a protection film Cap4. The TFTs are provided on the substrate 100 so as to correspond to a plurality of pixels, respectively. The light transmission film 204 is provided between the TFTs and the substrate 100. The protection film Cap4 covers an end surface 204b of the light transmission film 204, the end surface 204b being not parallel with the substrate 100. The TFT includes a gate electrode, a gate insulating film, a semiconductor film, a drain electrode, and a source electrode. The protection film Cap4 is arranged between the light transmission film 204 and the semiconductor film of the TFT.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: January 7, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shogo Murashige, Izumi Ishida, Tomohiro Kosaka, Tohru Okabe, Takeshi Hara, Hirohiko Nishiki
  • Publication number: 20190129267
    Abstract: Provided are an active-matrix substrate having a reliable line connection structure, a method for producing the same, and a display device including the same. A first metal line 122 and a second metal line 125 are electrically connected via an IGZO layer 124 rendered conductive. In this case, the second metal line 125 is isolated from an ITO layer 109 without contacting the ITO layer 109 because there are a passivation layer 107 and an organic insulating film 108 formed between the second metal line 125 and the ITO layer 109. Thus, no contact fault due to electric corrosion occurs between an aluminum layer 125a of the second metal line 125 and the ITO layer 109, whereby a reliable line connection structure is achieved.
    Type: Application
    Filed: May 2, 2017
    Publication date: May 2, 2019
    Inventors: Tohru OKABE, Hirohiko NISHIKI, Takeshi YANEDA
  • Publication number: 20190131322
    Abstract: A method for manufacturing a thin-film transistor that includes a source electrode and a drain electrode at least one of which has a layered structure of a plurality of metal layers including an Al layer and at least one layer made of a metal other than Al and a channel layer made of an oxide semiconductor includes forming a conductive film for the source electrode and the drain electrode, patterning the conductive film to form the source electrode and the drain electrode, forming a passivation film, and conducting heat treatment. The method includes preliminary heat treatment prior to the heat treatment, the preliminary heat treatment being conducted between the patterning of the conductive film and the formation of the passivation film.
    Type: Application
    Filed: October 26, 2018
    Publication date: May 2, 2019
    Inventors: Kazuatsu ITO, Hirohiko NISHIKI