Patents by Inventor Hirohito Watanabe

Hirohito Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5661052
    Abstract: The method of fabricating a semiconductor device, includes the steps of (a) forming gate oxides on regions separated by device isolation regions, (b) depositing an amorphous silicon or a polysilicon film, (c) depositing a removable space-forming film over the silicon film, (d) patterning the space-forming film and the silicon film into the same shape to form a gate electrode comprising the thus patterned space-forming film and silicon film, (e) depositing a silicon nitride film, (f) etching the silicon nitride film to form a first sidewall around a sidewall of the gate electrode, (g) depositing a silicon oxide film, (h) etching the silicon oxide film to form a second sidewall around and onto the first sidewall, (i) etching the space-forming film with hydrofluoric anhydride for removal so that the silicon film is exposed and the first sidewall remains unremoved, (j) forming source/drain regions, and (k) selectively depositing a refractory metal or metal silicide film on the silicon film and the source/drain re
    Type: Grant
    Filed: March 19, 1996
    Date of Patent: August 26, 1997
    Assignee: NEC Corporation
    Inventors: Ken Inoue, Makoto Sekine, Hirohito Watanabe, Ichirou Honma
  • Patent number: 5658417
    Abstract: In order to study an etching rate difference of a layer formed mainly with silicon dioxide on a wafer, a thermal oxide film (113) and layers of BSG (117), BPSG (125), and PSG (129) are laminated on a wafer and are etched in a gaseous etching atmosphere consisting essentially of hydrogen fluoride or a mixture of hydrogen fluoride and water vapor. The layers are etched with various etching rates which are higher than that of the thermal oxide film. The etching rate difference is a difference between the etching rate of each layer and an etching rate of the thermal oxide film. The layers may include impurities, such as boron and phosphorus, collectively as a part of a layer material of each layer. The etching rate difference depends on the layer material. Preferably, the gaseous etching atmosphere should have a reduced pressure. Alternatively, a water vapor partial pressure should not be greater than 2000 Pa. As a further alternative, either the layer or the gaseous etching atmosphere should be heated.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: August 19, 1997
    Assignees: NEC Corporation, ASM Japan K.K.
    Inventors: Hirohito Watanabe, Mitsusuke Kyogoku
  • Patent number: 5623243
    Abstract: A semiconductor device having a roughed surface, which is useful for a capacitor electrode is disclosed. The device is featured by depositing a polycrystalline silicon layer in such a manner that polycrystalline grains having a hemispherical like shape or a mushroom like shape are caused at the surface of the polycrystalline silicon layer. A dielectric is formed on the polycrystalline layer having an uneven surface. A conductive layer is formed on the dielectric layer. The semiconductor device thus obtained has a large effective surface area and is suitable for a capacitor electrode because of its increased effective surface area from the hemispherical like shaped or mushroom like shaped polycrystalline grains.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: April 22, 1997
    Assignee: NEC Corporation
    Inventors: Hirohito Watanabe, Toru Tatsumi
  • Patent number: 5397748
    Abstract: A thermal oxidation method for producing a semiconductor device having a capacitor insulating film structure capable of making a thin film having a small leakage current and small temperature dependence of the leakage current. In the insulating film, a silicon nitride film with a small electron mobility and a silicon oxide film with a small hole mobility are alternately laminated in order of the nitride film/oxide film/nitride film/oxide film from a lower electrode side. A current component such as electrons flowing in this insulating film structure is limited by the layer with the smaller mobility to reduce the leakage current. An oxide film thickness of approximately several .ANG. can thus be strictly controlled. By forming the silicon nitride film between the high dielectric oxide film and the electrode, the reaction of the silicon electrode and the high dielectric oxide film can be prevented.
    Type: Grant
    Filed: December 24, 1992
    Date of Patent: March 14, 1995
    Assignee: NEC Corporation
    Inventors: Hirohito Watanabe, Sadayuki Ohnishi
  • Patent number: 5372962
    Abstract: A capacitor incorporated in a semiconductor integrated circuit device is expected to have a large amount of capacitance without increase of the occupation area, and has a lower electrode increased in surface area by using a roughening technique selected from the group consisting of an anodizing technique, an anodic oxidation, a wet etching and a dry etching so that a surface of the lower electrode becomes porous, thereby increasing the capacitance.
    Type: Grant
    Filed: February 1, 1993
    Date of Patent: December 13, 1994
    Assignee: NEC Corporation
    Inventors: Toshiyuki Hirota, Ichirou Honma, Hirohito Watanabe, Masanobu Zenke
  • Patent number: 5366920
    Abstract: A thin film capacitor which comprises a lower electrode, a dielectric film and an upper electrode is fabricated on a substrate. The lower electrode is not provided by etching process using a photoresist mask, but it is provided by providing an aperture thorough an insulating layer deposited on the substrate, and depositing a conductive film on the bottom of the aperture and connected to a lower interconnection provided on the bottom of the aperture. Consequently, no convex protrusion is found at the processed edge of the lower electrode.
    Type: Grant
    Filed: April 12, 1994
    Date of Patent: November 22, 1994
    Assignee: NEC Corporation
    Inventors: Shintaro Yamamichi, Hirohito Watanabe, Toshiki Hashimoto, Toshiyuki Sakuma
  • Patent number: 5366917
    Abstract: A method for fabricating a polycrystalline silicon having a roughed surface, which is useful for a capacitor electrode is disclosed. The method is featured by depositing a polycrystalline silicon layer in such a manner that grains of silicon are caused at the surface of the polycrystalline silicon layer. The polycrystalline silicon layer thus obtained has a large effective surface area and is suitable fur a capacitor electrode because of its increased effective surface area.
    Type: Grant
    Filed: March 19, 1991
    Date of Patent: November 22, 1994
    Assignee: NEC Corporation
    Inventors: Hirohito Watanabe, Toru Tatsumi