Abstract: An electronic component in which an element is formed on a chip includes: a pad that is made of a conductive material and that is formed in a first bump formation region that is two-dimensionally arranged in center of one principle face and in a second bump formation region that is linearly arranged at peripheral border of the principle face; a passivation film that is formed on the principle face to cover portion except a formation position of the pad; a metal layer that is formed on the pad; and a bump that is made of a conductive material and that is formed on the metal layer by plating, wherein radius of the metal layer in the second bump formation region is smaller than radius of at least some of the metal layer in the first bump formation region.

Abstract: An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.

Abstract: A peripheral processing method includes: by at least one of locally heating the periphery of a workpiece including a silicon-based substrate and selectively supplying reacting activation species to the periphery, allowing oxidation rate on the periphery to be higher than oxidation rate of native oxide film on a surface of the silicon-based substrate, thereby forming a first oxide film along the periphery, the first oxide film being thicker than the native oxide film.

Abstract: An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.

Abstract: A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening at a predetermined position is formed on the first conducting layer. A second conducting layer is formed inside the opening of the mask layer. The mask layer is removed. A relocation wiring that includes the first conducting layer and electrically draws out the electrode terminal is formed by performing anisotropic etching for the first conducting layer using the second conducting layer as a mask. Finally, a bump is formed on the relocation wiring by causing the second conducting layer to reflow.

Abstract: According to an embodiment of the present invention, a method of manufacturing a semiconductor device, comprising forming a conducting layer on a substrate; forming a resist mask having an opening in a prescribed position on the conducting layer; forming a first plated film in the opening by supplying an electric current to the conducting layer; increasing the interval between an inner side surface of the resist mask forming the opening and the first plated film by setting back the inner side surface; and forming a second plated film in the opening resulting from the setback of the inner side surface to cover the first plated film by supplying an electric current to the conducting layer.

Abstract: A semiconductor device which is compact and thin in size, low in resistance of a current path and parasitic inductance and excellent in reliability is provided. This semiconductor device comprises a semiconductor substrate, a first main electrode which is formed on a front surface of the semiconductor substrate, a second main electrode which is formed on a rear surface of the semiconductor substrate, and a conducting portion which is formed in a direction to pierce through the semiconductor substrate, wherein the second main electrode is extracted to the front surface of the semiconductor substrate via the conducting portion. And, the conducting portion is a through via which has a through hole formed through the semiconductor substrate in its thickness direction and a conductive portion which is formed in the through hole and connected to the second main electrode.

Abstract: According to an embodiment of the present invention, a method of manufacturing a semiconductor device, comprising forming a conducting layer on a substrate; forming a resist mask having an opening in a prescribed position on the conducting layer; forming a first plated film in the opening by supplying an electric current to the conducting layer; increasing the interval between an inner side surface of the resist mask forming the opening and the first plated film by setting back the inner side surface; and forming a second plated film in the opening resulting from the setback of the inner side surface to cover the first plated film by supplying an electric current to the conducting layer.

Abstract: A semiconductor device is provided, including: a first barrier metal film provided by a PVD process in a recess formed in at least one insulating film, and containing at least one metal element belonging to any of the groups 4-A, 5-A, and 6-A; a second barrier metal film continuously provided by at least one of CVD and ALD processes on the first barrier metal film without being opened to atmosphere, and containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A; a third barrier metal film continuously provided by the PVD process on the second barrier metal film without being opened to the atmosphere, and containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A; and a first Cu film continuously provided on the third barrier metal film without being opened to the atmosphere and thereafter heated.

Abstract: There is here disclosed a manufacturing method of a semiconductor device, comprising providing a first film by a PVD process in a recess formed in at least one insulating film, the first film containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A, continuously providing a second film by at least one of CVD and ALD processes on the first film without opening to atmosphere, the second film containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A, continuously providing a third film by the PVD process on the second film without opening to the atmosphere, the third film containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A, continuously providing a first Cu film on the third film without opening to the atmosphere, and heating the Cu film.

Abstract: A peripheral processing method includes: by at least one of locally heating the periphery of a workpiece including a silicon-based substrate and selectively supplying reacting activation species to the periphery, allowing oxidation rate on the periphery to be higher than oxidation rate of native oxide film on a surface of the silicon-based substrate, thereby forming a first oxide film along the periphery, the first oxide film being thicker than the native oxide film.

Abstract: According to an aspect of the present invention, there is provided a bonding method, comprising disposing on a first body a second body with a bump interposed therebetween; and electrically and mechanically bonding the first body and the second body with the bump by passing a heating element between the first body and the second body to melt the bump by the heating element, the heating element being heated to a melting point or more of a material configuring the bump.

Abstract: According to an aspect of the present invention, there is provided a bonding method, comprising disposing on a first body a second body with a bump interposed therebetween; and electrically and mechanically bonding the first body and the second body with the bump by passing a heating element between the first body and the second body to melt the bump by the heating element, the heating element being heated to a melting point or more of a material configuring the bump.

Abstract: According to an embodiment of the present invention, a method of manufacturing a semiconductor device, comprising forming a conducting layer on a substrate; forming a resist mask having an opening in a prescribed position on the conducting layer; forming a first plated film in the opening by supplying an electric current to the conducting layer; increasing the interval between an inner side surface of the resist mask forming the opening and the first plated film by setting back the inner side surface; and forming a second plated film in the opening resulting from the setback of the inner side surface to cover the first plated film by supplying an electric current to the conducting layer.

Abstract: An insulating film formed on a conducting layer is dry-etched so as to make a connection hole in the insulating film to expose the conducting layer. Plasma is supplied onto the exposed conducting layer to dry-clean a damage layer produced in the connection hole. A product produced in the connection hole as a result of the dry cleaning is removed by a wet process. An oxide film formed in the connection hole as a result of the wet process is etched by a chemical dry process using a gas including either NF3 or HF. A thermally decomposable reaction product produced as a result of the etching is removed by heat treatment.

Abstract: A wafer supporting plate is formed of a glass or a resin which can permeate ultraviolet rays and has a nearly disk shape. An outer diameter of the wafer supporting plate is larger than that of the semiconductor wafer which is supported. In the wafer supporting plate, a plurality of openings are formed to correspond to plural through holes of the semiconductor wafer. The opening has an open area larger than an open area of the through hole, that is, has a larger diameter.

Abstract: A semiconductor device which is compact and thin in size, low in resistance of a current path and parasitic inductance and excellent in reliability is provided. This semiconductor device comprises a semiconductor substrate, a first main electrode which is formed on a front surface of the semiconductor substrate, a second main electrode which is formed on a rear surface of the semiconductor substrate, and a conducting portion which is formed in a direction to pierce through the semiconductor substrate, wherein the second main electrode is extracted to the front surface of the semiconductor substrate via the conducting portion. And, the conducting portion is a through via which has a through hole formed through the semiconductor substrate in its thickness direction and a conductive portion which is formed in the through hole and connected to the second main electrode.

Abstract: A semiconductor device comprises a semiconductor substrate having an through hole, a first insulation resin layer formed on an inner surface of the through hole, a second insulation resin layer formed on at least one of front and rear surfaces of the semiconductor substrate, and a first conductor layer formed in the through hole to connect at least both front and rear surfaces of the semiconductor substrate and insulated from the inner surface of the through hole with the first insulation resin layer. A second conductor layer (wiring pattern) which is electrically connected to the first conductor layer in the through hole is further provided on the second insulation resin layer. The conductor layer formed in the through hole and constituting a connecting plug has a high insulation reliability. Therefore, a semiconductor device suitable for a multi-chip package and the like can be obtained.

Abstract: There is provided an electroless Ni—B plating liquid for forming, a Ni—B alloy film on at least part of the interconnects of an electronic device having an embedded interconnect structure, the electroless Ni—B plating liquid comprising nickel ions, a complexing agent for nickel ions, a reducing agent for nickel ions, and ammonums (NH4+). The electroless Ni—B plating liquid can lower the boron content of the resulting plated film without increasing the plating rate and form a Ni—B alloy film having an FCC crystalline structure.

Abstract: There is here disclosed a manufacturing method of a semiconductor device, comprising providing a first film by a PVD process in a recess formed in at least one insulating film, the first film containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A, continuously providing a second film by at least one of CVD and ALD processes on the first film without opening to atmosphere, the second film containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A, continuously providing a third film by the PVD process on the second film without opening to the atmosphere, the third film containing at least one metal element belonging to any one of the groups 4-A, 5-A, and 6-A, continuously providing a first Cu film on the third film without opening to the atmosphere, and heating the Cu film.