Patents by Inventor Hirokazu Ezawa

Hirokazu Ezawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040251550
    Abstract: Disclosed is a semiconductor device comprising a porous film formed above a semiconductor substrate, the porous film having at least one burying concave selected from the group consisting of a trench and a hole, a conductive barrier layer formed on the inner surface of the burying concave, a conductive member buried in the burying concave with the conductive barrier layer interposed between the porous film and the conductive member, and a mixed layer formed between the porous film and the conductive barrier layer, and containing a component of the porous film and a component of the conductive barrier layer.
    Type: Application
    Filed: September 17, 2003
    Publication date: December 16, 2004
    Inventors: Takashi Yoda, Seiichi Omoto, Hisashi Kaneko, Hirokazu Ezawa
  • Publication number: 20040238955
    Abstract: After a copper diffusion preventing film 4 is formed on a copper pad 1, a barrier metal including a titanium film 5, a nickel film 6, and a palladium film 7 is formed on the copper diffusion preventing film 4. The copper diffusion preventing film formed on the copper pad suppresses diffusion of copper. Even when a solder bump is formed on the copper pad, diffusion of tin in the solder and copper is suppressed. This prevents formation of an intermetallic compound between copper and tin, so no interface de-adhesion or delamination occurs and a highly reliable connection is obtained. This structure can be realized by a simple fabrication process unlike a method of forming a thick barrier metal by electroplating. In this invention, high shear strength can be ensured by connecting a solder bump, gold wire, or gold bump to a copper pad without increasing the number of fabrication steps.
    Type: Application
    Filed: June 29, 2004
    Publication date: December 2, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Soichi Homma, Masahiro Miyata, Hirokazu Ezawa
  • Patent number: 6798050
    Abstract: After a copper diffusion preventing film 4 is formed on a copper pad 1, a barrier metal including a titanium film 5, a nickel film 6, and a palladium film 7 is formed on the copper diffusion preventing film 4. The copper diffusion preventing film formed on the copper pad suppresses diffusion of copper. Even when a solder bump is formed on the copper pad, diffusion of tin in the solder and copper is suppressed. This prevents formation of an intermetallic compound between copper and tin, so no interface de-adhesion or delamination occurs and a highly reliable connection is obtained. This structure can be realized by a simple fabrication process unlike a method of forming a thick barrier metal by electroplating. In this invention, high shear strength can be ensured by connecting a solder bump, gold wire, or gold bump to a copper pad without increasing the number of fabrication steps.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: September 28, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Homma, Masahiro Miyata, Hirokazu Ezawa
  • Publication number: 20040182277
    Abstract: There is provided an electroless Ni—B plating liquid for forming, a Ni—B alloy film on at least part of the interconnects of an electronic device having an embedded interconnect structure, the electroless Ni—B plating liquid comprising nickel ions, a complexing agent for nickel ions, a reducing agent for nickel ions, and ammonums (NH4+). The electroless Ni—B plating liquid can lower the boron content of the resulting plated film without increasing the plating rate and form a Ni—B alloy film having an FCC crystalline structure.
    Type: Application
    Filed: January 28, 2004
    Publication date: September 23, 2004
    Inventors: Hiroaki Inoue, Kenji Nakamura, Moriji Matsumoto, Hirokazu Ezawa, Masahiro Miyata, Manabu Tsujimura
  • Patent number: 6734568
    Abstract: A semiconductor device comprises an electrode formed above a substrate, an under bump metal (UBM) film on the electrode, the under bump metal film being in the shape of a recess, and a bump electrode embedded in the under bump metal film, the bump electrode having sides and bottom thereof surrounded by the under bump metal film.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: May 11, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mie Matsuo, Masahiro Miyata, Hirokazu Ezawa
  • Patent number: 6706422
    Abstract: There is provided an electroless Ni—B plating liquid for forming, a Ni—B alloy film on at least part of the interconnects of an electronic device having an embedded interconnect structure, the electroless Ni—B plating liquid comprising nickel ions, a complexing agent for nickel ions, a reducing agent for nickel ions, and ammonums (NH4+). The electroless Ni—B plating liquid can lower the boron content of the resulting plated film without increasing the plating rate and form a Ni—B alloy film having an FCC crystalline structure.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: March 16, 2004
    Assignees: Ebara Corporation, Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Inoue, Kenji Nakamura, Moriji Matsumoto, Hirokazu Ezawa, Masahiro Miyata, Manabu Tsujimura
  • Patent number: 6661088
    Abstract: A semiconductor integrated circuit device has a semiconductor chip, interposer, and substrate. The semiconductor chip has a plurality of first pads arranged at first pitches on a surface. The interposer has a first surface and a second surface. On the first surface, a plurality of second pads are arranged at the first pitches. On said second surface, a plurality of third pads arranged at second pitches which are larger than the first pitches. The second pads and the first pads are connected to each other by joining the first surface of the interposer to the surface of the semiconductor chip so as to face each other. The substrate has a plurality of fourth pads arranged at the second pitches on a surface. The fourth pads and the third pads are connected to each other by joining the surface of the substrate to the second surface of the interposer so as to face each other.
    Type: Grant
    Filed: September 26, 2000
    Date of Patent: December 9, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yoda, Hirokazu Ezawa
  • Patent number: 6605522
    Abstract: A present semiconductor device includes a plurality of bump electrodes formed over a semiconductor substrate to allow signals to be input and output to and from a semiconductor element. After the formation of the bump electrodes an organic insulting film is coated on the whole surface of a resultant wafer structure, followed by a drying, a solidifying and an etch-back step. By so doing, a top area of the bump electrode is more projected than a top area of the organic insulating film. A lead is connected by a pressure and heat to the top area of the bump electrode.
    Type: Grant
    Filed: July 27, 2000
    Date of Patent: August 12, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirokazu Ezawa, Masahiro Miyata
  • Patent number: 6569752
    Abstract: The present semiconductor element comprises a semiconductor substrate, a wiring pad formed thereon, a layer of barrier metal formed thereon, an intermetallic compound Ag3Sn formed thereon, and a protruded electrode consisting of low-melting metal formed thereon. In addition, a fabricating method of a semiconductor element comprises the steps of forming a wiring pad on a semiconductor substrate, forming a layer of barrier metal thereon, forming a metallic layer containing Ag thereon, forming a layer of low-melting metal containing Sn thereon, and melting the layer of low-melting metal containing Sn to form a protruded electrode and simultaneously to form an intermetallic compound Ag3Sn at an interface between the metallic layer containing Ag and the layer of low-melting metal containing Sn. Thus, with Pb-free solder, a semiconductor element of high reliability can be obtained.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: May 27, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Homma, Masahiro Miyata, Hirokazu Ezawa, Junichiro Yoshioka, Hiroaki Inoue, Tsuyoshi Tokuoka
  • Publication number: 20030052409
    Abstract: A semiconductor device comprises an electrode formed above a substrate, an under bump metal (UBM) film on the electrode, the under bump metal film being in the shape of a recess, and a bump electrode embedded in the under bump metal film, the bump electrode having sides and bottom thereof surrounded by the under bump metal film.
    Type: Application
    Filed: August 27, 2002
    Publication date: March 20, 2003
    Inventors: Mie Matsuo, Masahiro Miyata, Hirokazu Ezawa
  • Publication number: 20020140099
    Abstract: There is provided a semiconductor device comprising a semiconductor substrate, a first wiring formed above the semiconductor substrate and including a first polysilicon film containing a first conductivity type impurity and a first silicide film formed on the first polysilicon film and containing at least one of Co, Ni and Pd, a second wiring formed above the semiconductor substrate and including a second polysilicon film containing a second conductivity type impurity and connected to the first polysilicon film and a second silicide film formed on the second polysilicon film and containing at least one of Co, Ni and Pd, and a conductive connection member having a portion corresponding to a boundary region of the first polysilicon film and the second polysilicon film and connected to the first silicide film and the second silicide film.
    Type: Application
    Filed: March 28, 2002
    Publication date: October 3, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kaori Tsutsumi, Jota Fukuhara, Hirokazu Ezawa
  • Publication number: 20020100391
    Abstract: There is provided an electroless Ni—B plating liquid for forming, a Ni—B alloy film on at least part of the interconnects of an electronic device having an embedded interconnect structure, the electroless Ni—B plating liquid comprising nickel ions, a complexing agent for nickel ions, a reducing agent for nickel ions, and ammonums (NH4+). The electroless Ni—B plating liquid can lower the boron content of the resulting plated film without increasing the plating rate and form a Ni—B alloy film having an FCC crystalline structure.
    Type: Application
    Filed: November 28, 2001
    Publication date: August 1, 2002
    Inventors: Hiroaki Inoue, Kenji Nakamura, Moriji Matsumoto, Hirokazu Ezawa, Masahiro Miyata, Manabu Tsujimura
  • Patent number: 6407453
    Abstract: Disclosed is a semiconductor device, comprising a semiconductor substrate, an insulating layer and a metallic wiring layer formed on the semiconductor substrate; and an intermediate layer formed between the insulating layer and the metallic wiring layer in contact with both the insulating layer and the metallic wiring layer, wherein the intermediate layer contains the metallic material forming the metallic wiring layer, Si and O.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: June 18, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadayoshi Watanabe, Sachiyo Ito, Takamasa Usui, Hisashi Kaneko, Masako Morita, Hirokazu Ezawa
  • Patent number: 6404051
    Abstract: A semiconductor device includes at least one bump electrode for inputting and outputting signals to and from the semiconductor device. The bump electrode is positioned above a semiconductor substrate with an electrode pad and metal layer disposed therebetween. A resin film covers a surface of the semiconductor substrate except at a top area of the bump electrode. The bump electrode projects a sufficient distance above a top surface of the resin film so that heat induced defects are reduced and pressure exerted on a top area of the bump electrode is absorbed to suppress occurrence of cracks in the resin film.
    Type: Grant
    Filed: March 23, 1995
    Date of Patent: June 11, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirokazu Ezawa, Masahiro Miyata
  • Patent number: 5992725
    Abstract: An electronic element producing apparatus comprises a bonding tool 1 which has a first supply hole 2 for passing a bonding wire 3 used to bond a bonding pad 6 of a semiconductor device 5 and an external conductor which is to be connected electrically with the bonding pad 6, and contacts a leading end 3b of the bonding wire 3 protruded outside from the first supply hole 2 to the bonding pad 6, and which also has a second supply hole 12 to supply a bonding material to bond the bonding pad 6 and the leading end 3b of the bonding wire 3, the second supply hole 12 being formed to supply the conductive material to a contact point between the bonding wire 3 and the bonding pad 6. Therefore, the bonding pad 6 and the bonding wire 3 can be bonded without applying a dynamic or thermal load to the semiconductor device 5.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: November 30, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidemitsu Egawa, Hirokazu Ezawa
  • Patent number: 5885891
    Abstract: Disclosed is a method of manufacturing a semiconductor device, comprising the step of forming a pad electrode on an insulating film covering a semiconductor substrate, the step of forming a first metal layer on the pad electrode, the first metal layer being capable of forming a strong adhesive bond with the pad layer, followed by forming a second metal layer on the first metal layer, the second metal layer acting as a barrier layer and being capable of forming a strong adhesive bond with a solder, the step of forming a resist pattern on the second metal layer in a manner to cover that region which corresponds to the pad electrode, the step of etching the second metal layer using the resist pattern as a mask, the step of removing the resist pattern, the step of forming a solder layer selectively on the second metal layer, and the step of selectively etching the first metal layer using the solder layer as a mask.
    Type: Grant
    Filed: July 16, 1997
    Date of Patent: March 23, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Miyata, Hirokazu Ezawa
  • Patent number: 5705230
    Abstract: The improved method comprises contacting a substrate 5 at least once by a liquid containing the elements that compose a pure metal or an alloy with which the small holes or recesses 3a in the substrate 5 are to be filled or covered, whereby the liquid wets the inner surfaces of said small holes or recesses 3a while, at the same time, said pure metal or said alloy is deposited on the surface of said substrate 5. The method is capable of filling small holes or covering small recesses in the surface of the substrate 5 with improved efficiency while, at the same time, it improves the heat resistance and materials stability of the part that contains the formed filling or covering layer.
    Type: Grant
    Filed: October 17, 1994
    Date of Patent: January 6, 1998
    Assignee: Ebara Corporation
    Inventors: Toru Matanabe, Hirokazu Ezawa, Masahiro Miyata, Yukio Ikeda, Manabu Tsujimura, Hiroaki Inoue, Takeyuki Odaira, Naoaki Ogure
  • Patent number: 5656542
    Abstract: In a semiconductor device and a method for manufacturing the same according to the present invention, for example, an insulating film is deposited on a silicon substrate, and a concave groove is formed in the insulating film in accordance with a predetermined wiring pattern. Titanium and palladium are deposited in sequence on the insulating film to form a titanium film and a palladium film, respectively. A silver film is formed on the palladium film by electroplating, and a groove-shaped silver wiring layer is formed by polishing. The resultant structure is annealed at a temperature of about 700.degree. C., and an intermetallic compound is formed by alloying the titanium film and palladium film with each other. Consequently, a burying type wiring layer whose resistance is lower than that of aluminum, is constituted by the silver wiring layer and intermetallic compound.
    Type: Grant
    Filed: October 18, 1995
    Date of Patent: August 12, 1997
    Assignees: Kabushiki Kaisha Toshiba, Ebara Corporation
    Inventors: Masahiro Miyata, Hirokazu Ezawa, Naoaki Ogure, Manabu Tsujimura, Takeyuki Ohdaira, Hiroaki Inoue, Yukio Ikeda
  • Patent number: 5587337
    Abstract: A method of manufacturing bump electrodes with a larger top surface area than bottom surface area is disclosed. First, an organic layer is deposited. Then holes and grooves partially surrounding the holes are formed in the organic layer. Next, heat is applied to the organic film, causing the organic film to shrink. This causes the openings to expand at the top away from the grooves partially surrounding the holes. Metallic bumps are then deposited within the holes.
    Type: Grant
    Filed: May 19, 1995
    Date of Patent: December 24, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiaki Idaka, Hirokazu Ezawa
  • Patent number: RE37882
    Abstract: With a semiconductor device manufacturing method, a lower-layer interconnection is formed on a circuit board on which a plurality of semiconductor chips are mounted. Using a screen plate with openings corresponding to desired positions on the lower-layer interconnection, screen printing of a metal paste is effected, and the printed metal paste is dried and calcined by heat treatment to form a metal pillar on the lower-layer interconnection. An insulating film covering the lower-layer interconnection and the metal pillar is formed so that the tip of the metal pillar may be exposed. An upper-layer interconnection is formed on the insulating film so that this layer may contact with the exposed tip of the metal pillar.
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: October 15, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirokazu Ezawa, Masahiro Miyata