Patents by Inventor Hiroki Honda

Hiroki Honda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6418866
    Abstract: The objective of the present invention is to provide a fluidized bed incinerator which will increase the thermal capacity of the freeboard to respond to fluctuations of the load imposed by waste matter such as sludge or garbage with a high moisture content; which would absorb local and momentary temperature spikes due to load fluctuations or variations in the characteristics of the waste material.
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: July 16, 2002
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Yoshihito Shimizu, Hiroki Honda, Masao Takuma, Toshihisa Goda, Shiro Sasatani
  • Patent number: 6373106
    Abstract: In a MOS semiconductor device including a normal MOS transistor and an output MOS transistor for an input/output buffer, the normal MOS transistor is formed in a normal well. In an output MOS transistor, the channel region of the second MOS transistor and an element isolation region are formed in the region of a higher impurity concentration. On the other hand, the source and drain regions are formed in a lower impurity concentration region. Thereby, the source/drain capacitance of the output MOS transistor may be reduced, and the input/output capacitance of the semiconductor device may be reduced.
    Type: Grant
    Filed: March 28, 1997
    Date of Patent: April 16, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yukio Maki, Hiroki Honda
  • Publication number: 20020017749
    Abstract: A vibration, damping apparatus using a magnetic circuit which is easier and less expensive to manufacture than conventional apparatus is provided. The apparatus comprises a moving member 30 placed to move relatively away from and close to magnets 20 and 21 and made of a magnetic material which generates attraction force between the moving member 30 and the magnets 20 and 21, metal springs 40 and 41 as elastic members urging the moving member 30 in a direction in which the moving member 30 approaches thc magnets 20 and 21, and rubbers 60 end 61 as cushioning members mounted on predetermined positions to prevent the moving member 30 from coming in contact with the magnets 20 and 21.
    Type: Application
    Filed: July 5, 2001
    Publication date: February 14, 2002
    Inventors: Etsunori Fujita, Hiroki Oshimo, Hiroki Honda
  • Publication number: 20020003327
    Abstract: A magnetic spring device and a vibration damping apparatus, which are simpler and cheaper to manufacture, are disclosed. The magnetic spring device includes a plurality of stationary magnets, which are spaced apart to define a space between them, and a magnetic movable element, which is fit in the space. The magnetic poles of the stationary magnets are opposite to each other. The movable element is moved by the magnetic force generated by the stationary magnets in a parallel direction with the magnetic field. The properly positioned stationary magnets and movable element form a magnetic spring device, which together with additional properly positioned magnets alone may be used as a vibration damping apparatus. Also, when the magnetic spring device is combined with a cushioning member such as a metal spring, rubber or the like to form a vibration damping apparatus, the total elastic constant of the vibration damping apparatus may be near zero.
    Type: Application
    Filed: June 5, 2001
    Publication date: January 10, 2002
    Inventors: Yoshimi Enoki, Shigeki Wagata, Hiroki Oshimo, Etsunori Fujita, Hiroki Honda, Hideyuki Yamane
  • Publication number: 20020003262
    Abstract: In a MOS semiconductor device including a normal MOS transistor and an output MOS transistor for an input/output buffer, the normal MOS transistor is formed in a normal well. In an output MOS transistor, the channel region of the second MOS transistor and an element isolation region are formed in the region of a higher impurity concentration. On the other hand, the source and drain regions are formed in a lower impurity concentration region. Thereby, the source/drain capacitance of the output MOS transistor may be reduced, and the input/output capacitance of the semiconductor device may be reduced.
    Type: Application
    Filed: March 28, 1997
    Publication date: January 10, 2002
    Inventors: YUKIO MAKI, HIROKI HONDA
  • Patent number: 6271569
    Abstract: According to a semiconductor device and a method of manufacturing the same, a storage node has an increased capacity, and a resistance against soft error is improved. A GND interconnection is formed on a first interconnection layer including storage node portions with a dielectric film therebetween. Thereby, the storage node portions, the dielectric film, and the GND interconnection form a capacity element of the storage node portion. The first interconnection layer is arranged symmetrically around the center of the memory cell, and a plurality of memory cells having the same layout and neighboring to each other are arranged along the word lines.
    Type: Grant
    Filed: January 16, 1998
    Date of Patent: August 7, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshiyuki Ishigaki, Hiroki Honda
  • Patent number: 6236117
    Abstract: A semiconductor device including a shunt interconnection which operates at higher speed and permits high density integration is provided. In the semiconductor device including the shunt interconnection, a shunt connection region for a word line and a first shunt interconnection including a metal are formed in the memory cell region. In the memory cell region, shunt connection region and shunt interconnection are electrically connected with each other through a word line contact plug formed in a contact hole.
    Type: Grant
    Filed: March 26, 1998
    Date of Patent: May 22, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshiyuki Ishigaki, Hiroki Honda
  • Patent number: 6211036
    Abstract: The capacitor includes a first electrode which has a hollow structure formed by removal of a nitride film and which is formed from a conductive layer, and a second electrode which is formed from a conductive layer on the outside surface of the first electrode and on the surface of the hollow structure, while an insulating film is sandwiched between the first electrode and the second electrode. The capacitor prevents a short circuit from arising between a capacitor electrode and a wiring pattern in the proximity of the capacitor electrode in an oxide film serving as an interlayer insulating film.
    Type: Grant
    Filed: November 16, 1999
    Date of Patent: April 3, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Rui Morimoto, Hiroki Honda
  • Patent number: 6193503
    Abstract: The object of this invention is to provide an ash-melting furnace which can respond to fluctuations in the load and which will be capable of highly efficient and stable operation. In an ash-melting furnace which heats and melts the primary ash and the fly ash obtained by combustion together, this invention is characterized by supplying the primary ash (ash containing rough particles) from upper end of the furnace to form an upper layer of a two-tiered layer of ash, supplying the fly ash (ash containing minute particles) from an upper end of the furnace to form a lower layer of the two-tiered layer of ash, moving the two-tiered layer together towards the far end of the furnace, and heating and melting the two-tiered layer by a burner to form molten slugs during the moving step. When the burner is an oxygen-enriched burner, this configuration makes it possible to control the volume of oxygen to be added to the burner air (including changing the density of the oxygen).
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: February 27, 2001
    Assignee: Mitsubishi Heavy Industries Ltd.
    Inventors: Takehiro Kitta, Masao Takuma, Hiroki Honda, Kimitoshi Ose, Tetsuo Sato, Izuru Ishikawa, Kenichi Shibata, Akira Noma
  • Patent number: 6166465
    Abstract: A vibration generating mechanism includes at least first and second permanent magnets spaced from each other with the same magnetic poles opposed to each other. The first permanent magnet is coupled to a link mechanism so that the drive force of a drive source may be transmitted to the first permanent magnet via the link mechanism. A periodic and reciprocating movement of the first permanent magnet relative to the second permanent magnet changes the opposing area thereof, causing vibration of the second permanent magnet.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: December 26, 2000
    Assignee: Delta Tooling Co., Ltd.
    Inventors: Etsunori Fujita, Hiroki Honda
  • Patent number: 6162120
    Abstract: A control system registers effective combat actions of competitive characters in a RAM and learns the effective combat actions of the competitive characters. The control system also selects one of the combat actions stored in the RAM depending on the combat situation, and controls a CPU character to perform the selected combat action on a display screen. The CPU character learns and uses combat action information at the manual control level of the game player. Since the combating level of the CPU character is made substantially the same as the manual control level of the game player, the game player finds it enjoyable to play a combat game without getting bored.
    Type: Grant
    Filed: June 11, 1998
    Date of Patent: December 19, 2000
    Assignee: Konami Co., Ltd.,
    Inventors: Kazuya Takahashi, Hiroki Honda
  • Patent number: 6084329
    Abstract: A vibration mechanism having a magnetic spring includes a lower frame, an upper frame vertically movably mounted on the lower frame via a plurality of link mechanisms, and at least two permanent magnets mounted on the lower frame and the upper frame, respectively, with the same magnetic poles opposed to each other. A plurality of springs are connected to the link mechanisms to produce a lifting force of the upper frame. The total spring constant of the permanent magnets and the springs is partially set to a negative value or substantially zero.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: July 4, 2000
    Assignee: Delta Tooling Co., Ltd.
    Inventors: Etsunori Fujita, Yutaka Sakamoto, Hiroki Honda, Yasuhide Takata, Hiroki Ohshimo, Kazuyoshi Chizuka
  • Patent number: 6035980
    Abstract: A magnetic spring has at least two permanent magnets (2 and 4) spaced from each other in a kinetic mechanism. At the time of input and at the time of output, the geometric dimensions between the two permanent magnets are changed by the kinetic mechanism or an external force. The change in geometric dimensions is converted into a repulsive force in the kinetic mechanism, thereby (1) making the repulsive force from a balanced position of the two permanent magnets greater at the time of output than at the time of input, or (2) deriving a damping term of the magnetic spring to provide nonlinear damping and spring characteristics.
    Type: Grant
    Filed: December 8, 1997
    Date of Patent: March 14, 2000
    Assignee: Delta Tooling Co., Ltd.
    Inventors: Etsunori Fujita, Yoshimi Enoki, Hiroshi Nakahira, Seiji Kawasaki, Hiroki Honda, Yumi Ogura
  • Patent number: 5977597
    Abstract: A layout structure of an SRAM for reductions in the number of interconnect layers and in the number of connection holes with conventional advantages maintained is disclosed. Contact holes and fields which have been shared between cells vertically adjacent to each other in plan view are divided between the cells. The cells are then positioned in translated relation also in a bit line direction (D1). In a resultant region, first-level polysilicon interconnect layers (1G(G)) for a GND line and first-level polysilicon interconnect layers (1G(W)) for a word line are formed in parallel in a word line direction (D2). Connection holes (GK2, GK1) for connecting gate electrodes of driver transistors (DTr1, DTr2) and fields (FL) are also used for connection holes (GK3) for connecting the fields (FL) and the GND interconnect layers (1G(G)). Further, interconnect layers having a high power supply potential is formed on the interconnect layers (1G(G)).
    Type: Grant
    Filed: July 25, 1997
    Date of Patent: November 2, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hiroki Honda
  • Patent number: 5962913
    Abstract: A base region and an emitter region are formed at a surface of an n-well region (collector region). A contact hole reaching a portion of the surface of the collector region is formed, a contact hole reaching a portion of the surface of the emitter region is formed, and a contact hole reaching a portion of the surface of the base region is formed. A collector electrode, an emitter electrode and a base electrode are formed in the contact holes, respectively. Assuming that L represents a longitudinal length of the contact hole accommodating the emitter electrode and S represents a width thereof perpendicular to the longitudinal direction, a value of L/S is 10 or more. Thereby, a collector resistance of a bipolar transistor can be reduced, and a manufacturing cost can be reduced.
    Type: Grant
    Filed: April 24, 1996
    Date of Patent: October 5, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hiroki Honda
  • Patent number: 5959334
    Abstract: A bipolar transistor is formed by forming a base region continuing from a source/drain region of an MOS transistor, as a link base region, and forming an emitter region at a bit line contact hole by impurity implantation. Alternatively, the bipolar transistor is formed by forming an intrinsic base region and an emitter region at a bit line contact hole by impurity implantation. The intrinsic base region is made deeper than the source/drain region. Further, the impurity of the intrinsic base region is made different from that of the link base region.
    Type: Grant
    Filed: May 2, 1997
    Date of Patent: September 28, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yukio Maki, Hiroki Honda
  • Patent number: 5793670
    Abstract: A memory cell includes first and second driver transistors, first and second access transistors and first and second load elements, and in addition, first and second bipolar transistors. Accordingly, static noise margin is enlarged. The first bipolar transistor has its emitter formed in one of the source/drain regions of the first access transistor. The collector of the first bipolar transistor is the backgate terminal of the first access transistor. One of the source/drain regions of the first access transistor functions as the base of the first bipolar transistor. The same applies to the second bipolar transistor and the second access transistor. As the memory cell is structured in the above described manner, lower power supply potential can be used without the problem of latch up or increased area.
    Type: Grant
    Filed: October 21, 1996
    Date of Patent: August 11, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tomohisa Wada, Hirotoshi Sato, Hiroki Honda
  • Patent number: 5751053
    Abstract: A bipolar transistor, an nMOS transistor and pMOS transistor are formed at a main surface of a p-type semiconductor substrate. The bipolar transistor includes a collector layer, a base layer and an emitter layer. Collector layer located immediately under base layer contains impurity of n-type at a concentration not more than 5xl0.sup.18 cm.sup.-3. Base layer located immediately under emitter layer has a diffusion depth not more than 0.3 .mu.m. A semiconductor device including the bipolar transistor having the above structure is used in a circuit performing small amplitude operation. Thereby, it is possible to provide the semiconductor device having the bipolar transistor, which can be manufactured at a low cost and can operate at a high speed.
    Type: Grant
    Filed: June 9, 1997
    Date of Patent: May 12, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hiroki Honda
  • Patent number: 5744855
    Abstract: In a bipolar transistor of a type in which metal electrodes are formed in direct contact with a p-type external base region and an n-type collector region, respectively, an external base region surrounding an outer periphery of an n-type emitter region is formed. A metal electrode is formed on the emitter region with a polycrystalline silicon layer therebetween. Thereby, formation of a buried diffusion layer can be eliminated, and thus a manufacturing cost of the bipolar transistor can be reduced while achieving a high performance of the bipolar transistor.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: April 28, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yukio Maki, Hiroki Honda
  • Patent number: 5632211
    Abstract: A method of incinerating wastes while controlling the production of dioxins wherein water vapor or water is sprayed in the main combustion zone of an incinerator. An apparatus for practicing the method of waste incineration, including a line for supplying main combustion air, either alone or together with a line for supplying recycled combustion gas, to the incinerator from below its hearth, is provided with a line for supplying water vapor or water in communication with the line or lines.
    Type: Grant
    Filed: February 14, 1995
    Date of Patent: May 27, 1997
    Assignee: Mitsubishi Jukogyo Kabushiki Kaisha
    Inventors: Satoshi Okuno, Hirotami Yamamoto, Susumu Nishikawa, Hiroki Honda, Yoshinori Terasawa