Abstract: A tire 1 includes a tread portion 2, and how the tire is to be oriented when mounted to a vehicle is specified for the tire. The tread portion 2 has an outer tread edge T1, an inner tread edge T2, a first crown main groove 4, a second crown main groove 5, and three land portions demarcated by the first crown main groove 4 and the second crown main groove 5. The land portions include an outer shoulder land portion 7 demarcated between the outer tread edge T1 and the first crown main groove 4. The outer shoulder land portion 7 has a largest width in a tire axial direction among the three land portions. The outer shoulder land portion 7 has an outer shoulder lateral groove 20 and an outer shoulder sipe 21.

Abstract: A storage circuit includes: the array of a memory cell MC including a variable-resistance element; a conversion circuit that converts the resistance value of each memory cell into the signal level of an electric signal; a reference signal generation circuit that generates a reference signal common to a plurality of columns; a correction circuit that corrects one of the signal level of the reference signal and the signal level of the electric signal for each column of the array of the memory cell; and an RW circuit that determines data stored in the memory cell belonging to a corresponding column by comparing one of the reference level and the signal level of the electric signal, corrected by the correction circuit, and the other of the reference level and the signal level of the electric signal.

Abstract: A tire has a tread portion including a first land portion including first and second circumferential edges and and a tread surface. On the first land portion, curved grooves are provided in a tire circumferential direction. Each curved groove extends from a first end on the first circumferential edge side, terminates at a second end within the first land portion, and includes first and second curved portions and on the first end and second end sides, respectively. The first curved portion is an arc curve with a radius of curvature having a center on the first circumferential edge side of the curved groove. The second curved portion is an arc curve with a radius of curvature having a center on the second circumferential edge side of the curved groove.

Abstract: An outer surface TS of a tire 2 includes a tread surface T and a pair of side surfaces S. A plurality of arcs representing a contour of the tread surface T include a pair of crown arcs. A ratio of a radius CR1 of a first crown arc to a radius CR2 of a second crown arc is not less than 1.10 and not greater than 1.70. A total groove volume of a first circumferential groove 48 located in a zone from an equator to a first tread reference end TE1 is larger than a total groove volume of a second circumferential groove 50 located in a zone from the equator to a second tread reference end TE2.

Abstract: A storage circuit includes a memory cell array of memory cells each including a variable resistance type element, a resistance-voltage conversion circuit RTj to convert a resistance value of a memory cell MCij to be read to a data voltage, a reference circuit and RTR to generate a reference voltage, a sense amplifier to determine read data by receiving the data voltage and the reference voltage via first and second input terminals, respectively, and comparing both voltages with each other, and an analog buffer circuit arranged between the resistance-voltage conversion circuit RTj and a first input terminal of the sense amplifier or between the reference circuit and RTR and a second input terminal of the sense amplifier. Current driving capability of the analog buffer circuit is large.

Abstract: A storage circuit (11) includes memory cells (MCij), each of which includes an MTJ element, and reference cells (RCi), each of which includes a series circuit of an MTJ element set to a low-resistance state and a linear resistor (FR). A RW circuit (23j) that includes a sense amplifier is provided in each column of a memory cell array (21), and compares a data voltage on a corresponding bit line (BLj) with a reference voltage. The sense amplifier includes a pair of PMOS transistors to which the data voltage and the reference voltage are applied, a CMOS sense latch that is connected to a current path of the PMOS transistors.

Abstract: An integrated circuit device of the invention, includes: a first resistance variable memory element provided on a semiconductor substrate; a second resistance variable memory element provided on the semiconductor substrate; and a semiconductor circuit for controlling write and read of the first resistance variable memory element and the second resistance variable memory element, which is provided on the semiconductor substrate, in which the second resistance variable memory element has a write current that is smaller than a write current of the first resistance variable memory element, and the second resistance variable memory element is disposed farther from the semiconductor substrate than the first resistance variable memory element.

Abstract: A storage circuit includes: the array of a memory cell MC including a variable-resistance element; a conversion circuit that converts the resistance value of each memory cell into the signal level of an electric signal; a reference signal generation circuit that generates a reference signal common to a plurality of columns; a correction circuit that corrects one of the signal level of the reference signal and the signal level of the electric signal for each column of the array of the memory cell; and an RW circuit that determines data stored in the memory cell belonging to a corresponding column by comparing one of the reference level and the signal level of the electric signal, corrected by the correction circuit, and the other of the reference level and the signal level of the electric signal.

Abstract: The specimen container according to one or more embodiments may include: a container main body including an opening; a cap arranged to close the opening of the container main body and including a slit-formed portion in which a slit that allows an aspiration tube to pass therethrough is formed; and a contact portion provided in a position different from that of the slit and that is brought into contact with a peripheral surface of the aspiration tube at least while the aspiration tube is withdrawn from the slit.

Abstract: The specimen container according to one or more embodiments may include a container main body including an opening and a cap arranged to close the opening of the container main body and including a slit formed to allow an aspiration tube to pass therethrough. The cap according to one or more embodiments may include a slit-formed portion in which the slit is formed and an elastic portion provided to surround the slit-formed portion and that is elastically deformed to movably support the slit-formed portion.

Abstract: A tire has a tread portion including a first land portion including first and second circumferential edges and and a tread surface. On the first land portion, curved grooves are provided in a tire circumferential direction. Each curved groove extends from a first end on the first circumferential edge side, terminates at a second end within the first land portion, and includes first and second curved portions and on the first end and second end sides, respectively. The first curved portion is an arc curve with a radius of curvature having a center on the first circumferential edge side of the curved groove. The second curved portion is an arc curve with a radius of curvature having a center on the second circumferential edge side of the curved groove.

Abstract: An integrated circuit device of the invention, includes: a first resistance variable memory element provided on a semiconductor substrate; a second resistance variable memory element provided on the semiconductor substrate; and a semiconductor circuit for controlling write and read of the first resistance variable memory element and the second resistance variable memory element, which is provided on the semiconductor substrate, in which the second resistance variable memory element has a write current that is smaller than a write current of the first resistance variable memory element, and the second resistance variable memory element is disposed farther from the semiconductor substrate than the first resistance variable memory element.

Abstract: Disclosed is a testing apparatus comprising a disposal container body comprising: a first opening portion that faces upward to receive a used test piece dropped by a test piece transfer part of the testing apparatus, wherein the test piece transfer part is configured to transfer the used test piece to the first opening portion; and a second opening portion that faces laterally to receive a liquid waste and to which an end of a discharge pipe of the testing apparatus is inserted, wherein the discharge pipe is configured to transfer the liquid waste to the second opening portion.

Abstract: A covariance data creation apparatus configured to execute assembly calculations on a fuel assembly based on microscopic cross sections, the apparatus executing: a perturbation data generation step of deriving a plurality of perturbation quantities of the microscopic cross sections based on microscopic covariance data that is data regarding uncertainties of the microscopic cross sections, and generating microscopic perturbation data from the derived perturbation quantities of the microscopic cross sections; a macroscopic cross section derivation step of executing the assembly calculations based on the microscopic perturbation data generated at the perturbation data generation step, and deriving a plurality of macroscopic cross sections individually corresponding to the perturbation quantities of the microscopic cross sections; and a macroscopic covariance data generation step of generating macroscopic covariance data that is data regarding uncertainties of the macroscopic cross sections based on the macroscop

Abstract: Disclosed is a testing apparatus comprising a disposal container body comprising: a first opening portion that faces upward to receive a used test piece dropped by a test piece transfer part of the testing apparatus, wherein the test piece transfer part is configured to transfer the used test piece to the first opening portion; and a second opening portion that faces laterally to receive a liquid waste and to which an end of a discharge pipe of the testing apparatus is inserted, wherein the discharge pipe is configured to transfer the liquid waste to the second opening portion.

Abstract: A storage circuit (11) includes memory cells (MCij), each of which includes an MTJ element, and reference cells (RCi), each of which includes a series circuit of an MTJ element set to a low-resistance state and a linear resistor (FR). A RW circuit (23j) that includes a sense amplifier is provided in each column of a memory cell array (21), and compares a data voltage on a corresponding bit line (BLj) with a reference voltage. The sense amplifier includes a pair of PMOS transistors to which the data voltage and the reference voltage are applied, a CMOS sense latch that is connected to a current path of the PMOS transistors.

Abstract: A circuit design support system, a circuit design support method, a circuit design support program, and a recording medium having the program recorded thereon are provided by which a design can be performed in consideration of the stochastic operation of the stochastic operation element and the influence caused by the stochastic operation of the stochastic operation element on the operation reliability of the circuit can be evaluated.

Abstract: A memory circuit (11) includes: a memory cell (MCij) including a variable-resistance element in which a resistance value varies substantially between two levels; a resistance-voltage conversion circuit that converts the resistance value of a memory cell (MCij) to be read into a data voltage; a reference circuit (RCi) including a series circuit of a variable-resistance element and a linear resistor, the variable-resistance element including substantially the same configuration as the configuration of the variable-resistance element included in the memory cell MCij and being set to a lower resistance of two levels; a reference voltage conversion circuit that converts the resistance value of the reference circuit (RCi) into a reference voltage; and a sense amplifier (SA) that determines data stored in the memory cell (MCij) by comparing the data voltage with the reference voltage.