Abstract: A compound of the formula: 1

Abstract: This invention provides a compound of the formula (I): 1

Abstract: The object of the present invention is to provide a semiconductor memory device wherein analog data signal potential read out from a memory cell to bit-line (bit-line read-out potential) can be measured precisely. In this invention, a sense part circuit block 140 differentially amplifies data signal occurring on one of a pair of bit-lines (for example, bit-line BLNk, BLTk) in a memory cell array 110, and reference signal occurring on another of the pair, and data is read out. Bit-lines BLN1, BLT1, -, BLNn, BLTn are connected to a reference potential setup circuit block 150. Reference potential setup circuit 150 sets up potential assigned from outside of the device as potential of reference signal on bit-line. Bit-line read-out potential is indirectly obtained from the differential amplification result by controlling the reference potential with the reference potential setup circuit block 150.

Abstract: In a semiconductor memory device including a plurality of word lines, a plurality of pairs of bit lines, a plurality of memory cells, each connected between one of the word lines and one of the bit lines, and a plurality of sense amplifiers for amplifying the difference in potential between the pair of the bit lines, a plurality of offset circuits, is provided, for applying an offset voltage independent of voltages at the bit lines, to at least one of the pair of the bit lines to reduce the difference in potential between the pair of the bit lines before the sense amplifiers are operated.

Abstract: This invention provides a compound of the formula: ##STR1## and its pharmaceutically acceptable salts, wherein Ar.sup.1 is selected from the group having the formulae: ##STR2## wherein, R.sup.1 and R.sup.2 are independently hydrogen or C.sub.1 -C.sub.6 alkyl;W is (CH.sub.2).sub.a wherein n is from 1 to 3, or --CH.dbd.CH--;X is C.sub.1 -C.sub.6 alkoxy or halo C.sub.1 -C.sub.6 alkoxy; andAr.sup.2 is phenyl optionally substituted by halogen atom.These compounds are useful in the treatment of a gastrointestinal disorder, a central nervous system (CNS) disorder, an inflammatory disease, emesis, urinary incontinence, pain, migraine, sunburn, angiogenesis, diseases, disorders and adverse conditions caused by Helicobacter pylori, or the like in a mammalian subject, especially humans.

Abstract: This invention provides a compound of the formula: ##STR1## and its pharmaceutically acceptable salts, wherein Ar.sup.1 is selected from groups of the following formulae: ##STR2## wherein, R.sup.1 and R.sup.2 are independently hydrogen or C.sub.1 -C.sub.6 alkyl;W is (CH.sub.2).sub.n wherein n is from 1 to 3, or --CH.dbd.CH--;X is C.sub.1 -C.sub.6 alkoxy or halo C.sub.1 -C.sub.6 alkoxy; andAr.sup.2 is phenyl optionally substituted by halogen atom.These compounds are useful in the treatment of a gastrointestinal disorder, a central nervous system (CNS) disorder, an inflammatory disease, emesis, urinary incontinence, pain, migraine, sunburn, angiogenesis, diseases, disorders and adverse conditions caused by Helicobacter pylori, or the like in a mammalian subject, especially humans.

Abstract: A ferroelectric memory device hardly affected by variations in characteristic of a ferroelectric capacitor is provided. Capacitors in two dummy memory cells are used such that one capacitor is a ferroelectric capacitor and always outputs a voltage corresponding to "0" while the other capacitor outputs a voltage corresponding to a sensitivity of a sense amplifier, both of the voltages are collectively used as a reference voltage.

Abstract: It is an object of the invention to provide a method for generating a reference voltage by means of a sense amplifier in a ferroelectric memory device in a 1T1C type (One Transistor One Capacitor type). The directions of the polarizations of dummy cell DMC1 and DMC2 are set so that they are not inverted in case that data stored therein are read. Transistors T1 and T2 are added to the sense amplifier in order to make it be unbalanced, when a datum stored in a memory cell is read. In case that a datum stored in the memory cell is read, the transistor on the dummy cell side is on and that on the memory cell side is off. Widths of channels of T1 and T2 are selected so that an apparent reference voltage is slightly higher than a voltage read on a bit line in case that the polarization of the dummy cell is not inverted.

Abstract: A non-volatile ferroelectric memory cell supplies electric charge from the ferroelectric capacitor to one of bit lines so as to rise the bit line to one of a first potential level representative of logic "1" level and a second potential level representative of logic "0" level, and a reference voltage generator generates a reference voltage level exactly adjusted to the mid point between the first potential level and the second potential level by supplying electric charge from a dummy memory cell storing a dummy data bit of logic "1" level and another dummy memory cell storing a dummy data bit of logic "0" level to the other of the bit lines and an adjacent bit line.

Abstract: The ferroelectric memory device includes (A) at least one memory cell array, the memory cell array including (a) a plurality of memory cells arranged in row and column directions, each of the memory cells having a capacitive element and a transistor, the capacitive element having a ferroelectric film interposed between electrodes facing to each other, storing and retaining binary data in accordance with polarization of the ferroelectric film, one of a source and a drain of the transistor being electrically connected to one of the electrodes of the capacitive element, and (b) a plate line being electrically connected to the other of the electrodes of the capacitive element; and (B) an arrangement for arranging a voltage of the plate line to be fixed and activating the transistor so as to arrange a voltage at a junction of the transistor and the capacitive element to be the same as the voltage of the plate line.

Abstract: In a ferroelectric memory, when data is read out from a memory cell, for the purpose of minimizing a variation of the voltage on the pair of data signal lines caused by factor other than the current caused due to the polarization of the ferroelectric capacitor, the number of memory cells connected to each one data signal line is limited. Thus, a voltage not smaller than the coercive voltage can be applied between the opposing electrodes of the ferroelectric capacitor, with the result that a sufficient read-out signal voltage can be obtained.

Abstract: A ferroelectric memory includes a circuit for temporarily controlling a parasitic capacitance of a pair of data signal lines to an optimum value when data is read out from a memory cell, for the purpose of minimizing a variation of the voltage on the pair of data signal lines caused by factor other than the current caused due to the polarization of the ferroelectric capacitor. Thus, a voltage not smaller than the coercive voltage can be applied between the opposing electrodes of the ferroelectric capacitor, with the result that a sufficient read-out signal voltage can be obtained.

Abstract: A non-volatile ferroelectric memory device includes a plurality of memory cells provided in a matrix manner, each of which comprises a transistor having a gate and source and drain regions formed in a semiconductor region, and a ferroelectric capacitor having first and second electrodes and a ferroelectric layer interposed between the first and second electrodes. The second electrode is connected to one of the source and drain regions of the transistor.

Abstract: In a ferroelectric memory, when data is read out from a memory cell, a variation absorbing circuit minimizes a variation of the voltage on the pair of data signal lines caused by factor other than the current caused due to the polarization of the ferroelectric capacitor. Thus, a voltage not smaller than the coercive voltage can be applied between the opposing electrodes of the ferroelectric capacitor, with the result that a sufficient read-out signal voltage can be obtained.

Abstract: The invention provides a nonvolatile random-access memory using memory cells consisting of a ferroelectric capacitor and a switching transistor. The memory has two memory blocks each of which has memory cells arranged in rows and columns, word lines, bit lines, a plate line, sense amplifiers and reference voltage generators. The memory includes a plate line voltage control circuit which impresses supply voltage to the plate line of one memory block and ground potential to the plate line of the other memory block during a transition period preceding to read or write operation and then connects the two plate lines to thereby keep the connected plate lines at an intermediate voltage between supply voltage and ground potential. To retard fatigue of the ferroelectric material by repeated polarization in positive and negative directions, the memory can optionally be operated in a volatile mode.

Abstract: A nonvolatile ferroelectric memory device comprises a power supply and a memory cell array having a plurality of memory cells arranged in rows and columns and further comprises a plate-voltage level generator, a power supply voltage detector, and a protective control circuit. The plate-voltage level generator generates a plate voltage on a plate line connected to the one electrode of a ferroelectric capacitor of each memory cell. The power supply voltage detector detects a voltage of the power supply to generate a low-voltage detection signal when the power supply voltage is lower than a threshold voltage. The protective control circuit responsive to the low-voltage detection signal fixes the word lines at a grounding voltage level so as to protect the ferroelectric capacitor from a voltage change of the word line. The protective control circuit may fix the bit lines at the plate voltage level when the power supply voltage is lower than the threshold voltage.

Abstract: In a semiconductor device comprising on a semiconductor substrate (41) first and second input buffers (21), first and second input signal connections (25) supplying the input buffers from input signal pads (23) with input signals, respectively, each with a buffer input level, and first and second reference signal connections (29) supplying a reference signal from a reference signal pad (27) to the input buffers with buffer reference levels, respectively, a grounding pad (71) is laid near the reference signal pad and supplied with a ground level for the semiconductor device with a capacitor (73) connected between the semiconductor substrate and each reference signal connection near the reference signal pad and preferably with the reference signal connections laid geometrically parallel to the input signal connections.

Abstract: A semiconductor dynamic random access memory device is equipped with rows of redundant memory cells for replacing defective rows of regular memory cells therewith, and a redundant system associated with the rows of redundant memory cells is enabled in a test sequence for selectively energizing redundant word lines in response to external address signals so as to eliminate an address pointer only used in the test sequence.

Abstract: In a dynamic memory, a ground control circuit is provided for each one memory cell array, and includes a first ground control transistor connected between ground and a source of a grounding transistor in all selection read circuits associated to the corresponding memory cell array. A gate of the transistor is connected to receive a block selection signal which is brought into a selection level at a predetermined timing when the corresponding memory cell array includes a selected memory cell, so that the source of the grounding transistor in all the selection read circuits associated to the corresponding memory cell array are connected to the ground through the first ground control transistor. Two second ground control transistors having a current drive capacity smaller than that of the first ground control transistor, are connected in parallel to the first ground control transistor.

Abstract: Signal wirings are incorporated in a semiconductor integrated circuit device for propagating a multi-bit signal from an array of pads to input buffer circuits, and either wiring gap or wiring width is changed for canceling difference in time constant due to the different wiring lengths so that the component bits of the multi-bit signal concurrently arrive at the input buffer circuits.