Patents by Inventor Hiroki Miyashita
Hiroki Miyashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100027369Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.Type: ApplicationFiled: October 12, 2009Publication date: February 4, 2010Inventors: Yuichi OKUDA, Masaru KOKUBO, Yoshinobu NAKAGOME, Hideharu YAHATA, Hiroki MIYASHITA
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Patent number: 7602665Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.Type: GrantFiled: July 8, 2008Date of Patent: October 13, 2009Assignee: Renesas Technology Corp.Inventors: Yuichi Okuda, Masaru Kokubo, Yoshinobu Nakagome, Hideharu Yahata, Hiroki Miyashita
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Publication number: 20090046517Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example; which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.Type: ApplicationFiled: October 15, 2008Publication date: February 19, 2009Inventors: Binhaku TARUISHI, Hiroki MIYASHITA, Ken SHIBATA, Masashi HORIGUCHI
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Patent number: 7453738Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example; which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.Type: GrantFiled: July 6, 2005Date of Patent: November 18, 2008Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd.Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Publication number: 20080273404Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.Type: ApplicationFiled: July 8, 2008Publication date: November 6, 2008Inventors: Yuichi OKUDA, Masaru Kokubo, Yoshinobu Nakagome, Hideharu Yahata, Hiroki Miyashita
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Patent number: 7411805Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.Type: GrantFiled: December 12, 2005Date of Patent: August 12, 2008Assignee: Renesas Technology Corp.Inventors: Yuichi Okuda, Masaru Kokubo, Yoshinobu Nakagome, Hideharu Yahata, Hiroki Miyashita
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Publication number: 20070027237Abstract: A thickening additive comprises a xanthan gum. A paste including one or more of sodium alginate, pectin and sodium CMC is added to the xanthan gum.Type: ApplicationFiled: July 26, 2005Publication date: February 1, 2007Inventors: Hiromitsu Hamano, Yuji Uzuhashi, Hiroki Miyashita
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Patent number: 7072242Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.Type: GrantFiled: October 18, 2004Date of Patent: July 4, 2006Assignee: Renesas Technology Corp.Inventors: Yuichi Okuda, Masaru Kokubo, Yoshinobu Nakagome, Hideharu Yahata, Hiroki Miyashita
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Publication number: 20060087909Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.Type: ApplicationFiled: December 12, 2005Publication date: April 27, 2006Inventors: Yuichi Okuda, Masaru Kokubo, Yoshinobu Nakagome, Hideharu Yahata, Hiroki Miyashita
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Publication number: 20050243644Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example; which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.Type: ApplicationFiled: July 6, 2005Publication date: November 3, 2005Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Patent number: 6954384Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.Type: GrantFiled: July 5, 2002Date of Patent: October 11, 2005Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd.Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Publication number: 20050052944Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.Type: ApplicationFiled: October 18, 2004Publication date: March 10, 2005Inventors: Yuichi Okuda, Masaru Kokubo, Yoshinobu Nakagome, Hideharu Yahata, Hiroki Miyashita
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Patent number: 6819626Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.Type: GrantFiled: July 8, 2003Date of Patent: November 16, 2004Assignee: Renesas Technology Corp.Inventors: Yuichi Okuda, Masaru Kokubo, Yoshinobu Nakagome, Hideharu Yahata, Hiroki Miyashita
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Clock generation circuit, control method of clock generation circuit and semiconductor memory device
Patent number: 6703879Abstract: A clock generation circuit including a clock duty adjusting circuit in the subsequent stage of a variable delay circuit to control the delay of the variable delay circuit with the rising edge of an external clock. When the phase of the rising edge is matched with the reference clock, the duty of an output clock is matched with the duty of the reference clock by adjusting the pulse width of the signal with the duty adjusting circuit at the falling edge.Type: GrantFiled: July 20, 2001Date of Patent: March 9, 2004Assignees: Renesas Technology Corporation, Hitachi Device Engineering Co., Ltd.Inventors: Yuichi Okuda, Hideo Chigasaki, Hiroki Miyashita -
Patent number: 6677791Abstract: A DLL circuit or the like is configured so as to be capable of measuring the optimum number of cycles for a delay amount from the input of an external clock to the output of data through the use of a variable delay circuit and performing lock according to the measured number of cycles, whereby a clock generation circuit having a wide lock range can be implemented regardless of the performance of the variable delay circuit and a clock access time.Type: GrantFiled: July 25, 2002Date of Patent: January 13, 2004Assignees: Renesas Technology Corporation, Hitachi Device Engineering Co., Ltd.Inventors: Yuichi Okuda, Hideo Chigasaki, Hiroki Miyashita
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Publication number: 20040004902Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.Type: ApplicationFiled: July 8, 2003Publication date: January 8, 2004Applicant: Hitachi, Ltd.Inventors: Yuichi Okuda, Masaru Kokubo, Yoshinobu Nakagome, Hideharu Yahata, Hiroki Miyashita
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Patent number: 6594197Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.Type: GrantFiled: July 1, 2002Date of Patent: July 15, 2003Assignee: Hitachi, Ltd.Inventors: Yuichi Okuda, Masaru Kokubo, Yoshinobu Nakagome, Hideharu Yahata, Hiroki Miyashita
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Publication number: 20030063519Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.Type: ApplicationFiled: July 1, 2002Publication date: April 3, 2003Applicant: Hitachi, Ltd.Inventors: Yuichi Okuda, Masaru Kokubo, Yoshinobu Nakagome, Hideharu Yahata, Hiroki Miyashita
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Patent number: 6496403Abstract: Disclosed a semiconductor memory device in which an access to a memory cell is designated according to a command, and a common data terminal is used as an input terminal to which a write signal to the memory cell is input and an output terminal from which a read signal from the memory cell is output. The semiconductor memory device includes: a first input circuit having input capacitance corresponding to the input terminal to which the command is input; and a second input circuit having input capacitance corresponding to the data terminal. A mask signal for checking the write signal input from the data terminal is input by either the first or second input circuit by a bonding option technique.Type: GrantFiled: July 18, 2001Date of Patent: December 17, 2002Assignee: Hitachi, Ltd.Inventors: Hiromasa Noda, Sadayuki Okuma, Hiroshi Ichikawa, Hiroki Miyashita, Yasushi Takahashi
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Publication number: 20020180500Abstract: A DLL circuit or the like is configured so as to be capable of measuring the optimum number of cycles for a delay amount from the input of an external clock to the output of data through the use of a variable delay circuit and performing lock according to the measured number of cycles, whereby a clock generation circuit having a wide lock range can be implemented regardless of the performance of the variable delay circuit and a clock access time.Type: ApplicationFiled: July 25, 2002Publication date: December 5, 2002Inventors: Yuichi Okuda, Hideo Chigasaki, Hiroki Miyashita