Patents by Inventor Hiroki Miyashita
Hiroki Miyashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20020163846Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instructions for the memory unit is provided, the data input buffer is rendered active in advance before the instructions for the write operation is provided, whereby wastefully consumed power is reduced.Type: ApplicationFiled: July 5, 2002Publication date: November 7, 2002Applicant: Hitachi, Ltd.Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Patent number: 6463008Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.Type: GrantFiled: January 7, 2002Date of Patent: October 8, 2002Assignee: Hitachi, Ltd.Inventors: Yuichi Okuda, Masaru Kokubo, Yoshinobu Nakagome, Hideharu Yahata, Hiroki Miyashita
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Patent number: 6455090Abstract: There is provided a liquid additive thickener, or a liquid thickening agent, which can thicken easily when it is added to an object. The liquid additive thickener comprises a liquid that is prepared by dissolving a thickening agent into water and is initially inhibited from forming viscous solutions or gels. The liquid can begin to form a viscous solution when it is added to a water-containing object. The liquid may be: (a) prepared to have a low viscosity by dissolving a thickening agent into water together with a poor solvent; (b) prepared to have a low viscosity by dissolving a thickening agent into water together with a low viscous saccharide; or (c) prepared to have a low viscosity by dissolving a thickening agent into water together with a reactive ion.Type: GrantFiled: January 28, 2000Date of Patent: September 24, 2002Assignee: INA Food Industry Co., Ltd.Inventors: Yuji Uzuhashi, Hiroki Miyashita
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Patent number: 6437619Abstract: A DLL circuit or the like is configured so as to be capable of measuring the optimum number of cycles for a delay amount from the input of an external clock to the output of data through the use of a variable delay circuit and performing lock according to the measured number of cycles, whereby a clock generation circuit having a wide lock range can be implemented regardless of the performance of the variable delay circuit and a clock access time.Type: GrantFiled: July 13, 2001Date of Patent: August 20, 2002Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Yuichi Okuda, Hideo Chigasaki, Hiroki Miyashita
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Patent number: 6424590Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instructions for the memory unit is provided, the data input buffer is rendered active in advance before the instructions for the write operation is provided, whereby wastefully consumed power is reduced.Type: GrantFiled: December 21, 2001Date of Patent: July 23, 2002Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Publication number: 20020085442Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.Type: ApplicationFiled: January 7, 2002Publication date: July 4, 2002Applicant: Hitachi, Ltd.Inventors: Yuichi Okuda, Masaru Kokubo, Yoshinobu Nakagome, Hideharu Yahata, Hiroki Miyashita
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Publication number: 20020054516Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instructions for the memory unit is provided, the data input buffer is rendered active in advance before the instructions for the write operation is provided, whereby wastefully consumed power is reduced.Type: ApplicationFiled: December 21, 2001Publication date: May 9, 2002Applicant: Hitachi, Ltd.Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Patent number: 6377511Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.Type: GrantFiled: July 31, 2000Date of Patent: April 23, 2002Assignee: Hitachi, Ltd.Inventors: Yuichi Okuda, Masaru Kokubo, Yoshinobu Nakagome, Hideharu Yahata, Hiroki Miyashita
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Publication number: 20020017939Abstract: A DLL circuit or the like is configured so as to be capable of measuring the optimum number of cycles for a delay amount from the input of an external clock to the output of data through the use of a variable delay circuit and performing lock according to the measured number of cycles, whereby a clock generation circuit having a wide lock range can be implemented regardless of the performance of the variable delay circuit and a clock access time.Type: ApplicationFiled: July 13, 2001Publication date: February 14, 2002Inventors: Yuichi Okuda, Hideo Chigasaki, Hiroki Miyashita
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Publication number: 20020012285Abstract: Disclosed a semiconductor memory device in which an access to a memory cell is designated according to a command, and a common data terminal is used as an input terminal to which a write signal to the memory cell is input and an output terminal from which a read signal from the memory cell is output. The semiconductor memory device includes: a first input circuit having input capacitance corresponding to the input terminal to which the command is input; and a second input circuit having input capacitance corresponding to the data terminal. A mask signal for checking the write signal input from the data terminal is input by either the first or second input circuit by a bonding option technique.Type: ApplicationFiled: July 18, 2001Publication date: January 31, 2002Applicant: Hitachi, Ltd.Inventors: Hiromasa Noda, Sadayuki Okuma, Hiroshi Ichikawa, Hiroki Miyashita, Yasushi Takahashi
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Clock generation circuit, control method of clock generation circuit and semiconductor memory device
Publication number: 20020008558Abstract: A clock duty adjusting circuit is provided in the subsequent stage of a variable delay circuit to control the delay of the variable delay circuit with the rising edge of clock. When the phase of the rising edge is matched with the reference clock, the duty of output clock is matched with the duty of the reference clock by adjusting the pulse width of the signal with the duty adjusting circuit at the falling edge.Type: ApplicationFiled: July 20, 2001Publication date: January 24, 2002Inventors: Yuichi Okuda, Hideo Chigasaki, Hiroki Miyashita -
Patent number: 6339552Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.Type: GrantFiled: August 18, 2000Date of Patent: January 15, 2002Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
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Patent number: 5392250Abstract: In a semiconductor memory device of the present invention, data read from a memory cell to a pair of complementary data lines or a pair of common data lines are fed directly to an output circuit not through any sense amplifier. As a result, the delay time of the sense amplifier itself is omitted from the address access time of the conventional semiconductor memory device using the sense amplifier, so that the semi-conductor memory device of the present invention can have its address access time made shorter than that of the conventional semiconductor memory device.Type: GrantFiled: January 15, 1993Date of Patent: February 21, 1995Assignee: Hitachi, Ltd.Inventors: Kinya Mitsumoto, Yoshikazu Iida, Hiroki Miyashita, Kazunori Onozawa