Patents by Inventor Hiroki Murakami

Hiroki Murakami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11656159
    Abstract: The present invention relates to a clearing technique which uses a solution containing at least one of a compound having a delipidation ability, a compound having a biochrome decoloring ability, a compound having a decalcification ability, a compound having a refractive index adjusting ability, and a compound having a tissue swelling ability. The clearing technique is suitable for use in high-throughput and low-magnification imaging which involves a simple process.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: May 23, 2023
    Assignee: RIKEN
    Inventors: Hiroki Ueda, Kazuki Tainaka, Tatsuya Murakami
  • Publication number: 20230146375
    Abstract: A substrate processing method of etching a SiN film formed on the substrate includes supplying a HF gas at a processing temperature of 450 degrees C. or higher to etch the SiN film.
    Type: Application
    Filed: March 17, 2021
    Publication date: May 11, 2023
    Inventors: Hiroki MURAKAMI, Masanobu MATSUNAGA, Yamato TONEGAWA
  • Publication number: 20230135342
    Abstract: A film forming method includes: preparing a substrate having a surface on which a first film containing boron and a second film made of a material different from that of the first film are formed; supplying a raw material gas, which contains halogen and an element X other than halogen, to the surface of the substrate; and supplying a plasmarized reaction gas, which contains oxygen, to the surface of the substrate, wherein a third film as an oxide film of the element X is selectively formed on the second film with respect to the first film by alternately supplying the raw material gas and the plasmarized reaction gas.
    Type: Application
    Filed: October 31, 2022
    Publication date: May 4, 2023
    Inventors: Sena FUJITA, Hiroki MURAKAMI
  • Publication number: 20230128868
    Abstract: A substrate processing method of etching an etching target film formed on a substrate includes: preparing the substrate having the etching target film; and etching the etching target film, wherein the etching the etching target film includes repeating, a plurality of times, supplying an etchant gas, and plasma-exciting a reaction gas to expose the substrate to plasma of the reaction gas.
    Type: Application
    Filed: March 2, 2021
    Publication date: April 27, 2023
    Inventors: Hiroki MURAKAMI, Shuichiro SAKAI
  • Publication number: 20230097923
    Abstract: Provided is a numerical control device for improving cycle time and machined surface quality.
    Type: Application
    Filed: February 26, 2021
    Publication date: March 30, 2023
    Applicant: FANUC CORPORATION
    Inventor: Hiroki MURAKAMI
  • Publication number: 20230087732
    Abstract: Disclosed is a voltage generating circuit including a reference voltage generating part, a leakage current monitoring part, a control part, and an internal voltage generating part. The reference voltage generating part generates a reference voltage. The leakage current monitoring part generates a monitoring leakage current corresponding to a leakage current of an internal circuit of a semiconductor device. The control part controls the reference voltage according to the monitoring leakage current. The internal voltage generating part receives the reference voltage being controlled by the control part, and supplies an internal voltage to the internal circuit according to the controlled reference voltage. A semiconductor device including the same is also disclosed.
    Type: Application
    Filed: June 22, 2022
    Publication date: March 23, 2023
    Applicant: Winbond Electronics Corp.
    Inventor: Hiroki Murakami
  • Publication number: 20230085298
    Abstract: An object of the present invention is to provide a composition for promoting sleep, that enables an increase of the sleep amounts in the overall night and in the initial stage of the night, a decrease of the sleep onset latent time, and an increase of the length of a sleep episode, and that is excellent in the stability and the safety. Another object of the present invention is to provide a food, a drug, and a feed that each include the composition for promoting sleep. The composition for promoting sleep is characterized in that the composition for promoting sleep includes a microorganism belonging to either Bifidobacterium adolescentis or Lactobacillus plantarum, or a culture thereof as an active ingredient.
    Type: Application
    Filed: January 26, 2021
    Publication date: March 16, 2023
    Inventors: Hiroki MURAKAMI, Taro KO, Hiroshi ISHIMOTO, Azusa KAMIKOUCHI, Ikue MORI
  • Patent number: 11489385
    Abstract: A rotor includes: a plurality of permanent magnets divided at regular intervals in a circumferential direction around a shaft, and provided in an axial direction; a first protection ring for positioning and holding ends in the axial direction of the permanent magnets; a second protection ring for positioning and holding other ends in the axial direction of the permanent magnets; and a protection cover covering outer circumferential surfaces of the permanent magnets, the first protection ring, and the second protection ring, and having a uniform thickness in a radial direction.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: November 1, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hiroki Murakami, Yoshiki Okada, Yoshiharu Takashima
  • Patent number: 11474493
    Abstract: To smoothen a machining route more appropriately. A numerical controller of the present invention comprises: a machining program look-ahead unit that acquires a program for machining; a command route mathematization unit that expresses a machining route as a parametric line segment or curve on the basis of the program for the machining; and a smoothing processing unit that sets a range of smoothing for a target point of the smoothing along the parametric line segment or curve in an optional range from the target point, and performs the smoothing on the target point on the basis of the set range of the smoothing. The range of the smoothing set by the smoothing processing unit is a range in which a deviation between before the smoothing and after the smoothing on the target point is a set threshold or less.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: October 18, 2022
    Assignee: FANUC CORPORATION
    Inventor: Hiroki Murakami
  • Publication number: 20220328301
    Abstract: In a mask pattern forming method, a resist film is formed over a thin film, the resist film is processed into resist patterns having a predetermined pitch by photolithography, slimming of the resist patterns is performed, and an oxide film is formed on the thin film and the resist patterns after an end of the slimming step in a film deposition apparatus by supplying a source gas and an oxygen radical or an oxygen-containing gas. In the mask pattern forming method, the slimming and the oxide film forming are continuously performed in the film deposition apparatus.
    Type: Application
    Filed: June 23, 2022
    Publication date: October 13, 2022
    Inventors: Kazuhide HASEBE, Shigeru NAKAJIMA, Jun OGAWA, Hiroki MURAKAMI
  • Patent number: 11462126
    Abstract: A control device is provided with: a posture information storage unit that stores posture associated information associated with workability being an evaluation criterion at a time of a posture for each piece of posture information of an operator; a posture information detection unit that acquires posture information of the operator during work as current posture information; a posture information calculation unit that obtains, from the posture associated information, ideal posture information for making improvement on workability of the current posture information, obtained by referring to the posture associated information in the storage unit from the current posture information; and a posture information notification unit that notifies the ideal posture information obtained by the calculation unit as an improvement proposal.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: October 4, 2022
    Assignee: Hitachi, Ltd.
    Inventors: Akihide Tanaka, Masanori Miyagi, Kazumichi Hosoya, Hiroki Murakami, Masao Shimizu
  • Patent number: 11435220
    Abstract: A combination weighing device includes: a conveyance unit; a plurality of first hoppers each receiving the article; a plurality of second hoppers detachably provided on a downstream side of the plurality of first hoppers, and each receiving the article; a weighing unit weighing the article held in each of the plurality of second hoppers; and a control unit performing combination calculation and discharging the article from the second hopper corresponding to the combination. The control unit performs combination calculation based on a weighing value corresponding to mass of the article held in each of the plurality of second hopper, and continues combination calculation based on a weighing value corresponding to mass of the article held in each of the second hoppers other than a part of the second hoppers in a state in which the part of the plurality of second hoppers has been removed.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: September 6, 2022
    Assignee: Ishida Co., Ltd.
    Inventors: Satoru Kamigaito, Hiroki Murakami
  • Patent number: 11404272
    Abstract: In a mask pattern forming method, a resist film is formed over a thin film, the resist film is processed into resist patterns having a predetermined pitch by photolithography, slimming of the resist patterns is performed, and an oxide film is formed on the thin film and the resist patterns after an end of the slimming step in a film deposition apparatus by supplying a source gas and an oxygen radical or an oxygen-containing gas. In the mask pattern forming method, the slimming and the oxide film forming are continuously performed in the film deposition apparatus.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: August 2, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Shigeru Nakajima, Jun Ogawa, Hiroki Murakami
  • Patent number: 11404271
    Abstract: In a mask pattern forming method, a resist film is formed over a thin film, the resist film is processed into resist patterns having a predetermined pitch by photolithography, slimming of the resist patterns is performed, and an oxide film is formed on the thin film and the resist patterns after an end of the slimming step in a film deposition apparatus by supplying a source gas and an oxygen radical or an oxygen-containing gas. In the mask pattern forming method, the slimming and the oxide film forming are continuously performed in the film deposition apparatus.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 2, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhide Hasebe, Shigeru Nakajima, Jun Ogawa, Hiroki Murakami
  • Patent number: 11380538
    Abstract: A nitride film forming method includes repeating a cycle a plurality of times, wherein the cycle includes: forming a layer containing an element to be nitrided on a substrate by supplying a source gas including the element to the substrate; plasmarizing a modifying gas including a hydrogen gas, and modifying the layer containing the element with the plasmarized modifying gas; and activating a nitriding gas including nitrogen by heat, and thermally nitriding the layer containing the element with the nitriding gas activated by heat.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: July 5, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hiroki Murakami
  • Publication number: 20220189778
    Abstract: A method of selectively forming a film on a substrate includes: a preparation process of preparing a substrate having a surface to which a metal film and an insulating film are exposed; a first removal process of removing a natural oxide film on the metal film; a first film forming process of forming a self-assembled monolayer, which suppresses formation of a titanium nitride film, on the insulating film by providing the substrate with a compound for forming the self-assembled monolayer, the compound having a functional group containing fluorine and carbon; a second film forming process of forming a titanium nitride film on the metal film; an oxidation process of oxidizing the surface of the substrate; and a second removal process of removing a titanium oxide film, which is formed on the metal film and the self-assembled monolayer, by providing the surface of the substrate with the compound.
    Type: Application
    Filed: February 28, 2020
    Publication date: June 16, 2022
    Inventors: Shinichi IKE, Shuji AZUMO, Yumiko KAWANO, Hiroki MURAKAMI
  • Publication number: 20220189777
    Abstract: A film formation method includes: providing a substrate including a first region in which a first material is exposed and a second region in which a second material different from the first material is exposed; forming a target film selectively in the first region among the first region and the second region; and removing a product produced in the second region in the forming the target film by supplying ClF3 gas to the substrate.
    Type: Application
    Filed: March 4, 2020
    Publication date: June 16, 2022
    Inventors: Yumiko KAWANO, Shuji AZUMO, Hiroki MURAKAMI
  • Publication number: 20220157616
    Abstract: A substrate processing method includes: (a) carrying a substrate having a first film with a recess, and a mask into a first chamber; (b) adjusting the substrate temperature to 200° C. or higher; (c-1) supplying silicon-containing reactive species into the first chamber, thereby adsorbing the species onto the side wall of the recess; and (c-2) supplying nitrogen-containing reactive species into the first chamber, thereby forming a second film on the side wall of the recess; (d) carrying the substrate into a second chamber; and (e) adjusting the substrate temperature to 100° C. or lower; and (f) etching the bottom of the recess. Further, (a) to (f) are repeated in this order until an aspect ratio of a depth dimension from the opening of the mask to the bottom of the recess becomes 50 or more.
    Type: Application
    Filed: November 17, 2021
    Publication date: May 19, 2022
    Applicant: Tokyo Electron Limited
    Inventors: Kae KUMAGAI, Ryutaro SUDA, Maju TOMURA, Kenji OUCHI, Hiroki MURAKAMI, Munehito KAGAYA, Shuichiro SAKAI
  • Patent number: 11322365
    Abstract: There is provided a substrate processing method including: reducing an oxide of a ruthenium film by supplying a hydrogen-containing gas to a substrate including the ruthenium film; etching the ruthenium film by supplying an oxygen-containing gas to the substrate so as to oxidize the ruthenium film; and repeating, multiple times, a cycle including reducing the oxide of the ruthenium film and etching the ruthenium film.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: May 3, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hiroki Murakami
  • Patent number: 11323067
    Abstract: The present invention provides an oscillator circuit and a semiconductor integrated circuit, which can suppress the upper limit of the frequency of a clock signal due to an error of the constant current circuit. The oscillator circuit of the present invention includes a constant current circuit, an oscillator, and a current limiting circuit. The constant current circuit generates a first output current according to a supply voltage. The current limiting circuit receives the first output current and generates a second output current, and establishes an upper limit for the second output current when the supply voltage drops below a lower limit of a guaranteed operational range of the constant current circuit. The oscillator generates a clock signal according to the second output current. By establishing the upper limit for the second output current, the upper limit of the frequency of the clock signal can be suppressed.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: May 3, 2022
    Assignee: WINDBOND ELECTRONICS CORP.
    Inventors: Masafumi Nakatani, Hiroki Murakami