Patents by Inventor Hiroki Nakamura

Hiroki Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9583630
    Abstract: A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate, and forming a first insulating film; a second step of forming a second insulating film, and forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; a third step of forming a second hard mask on a side wall of the first hard mask, and etching a second polysilicon so as to be left on side walls of the first dummy gate and the pillar-shaped semiconductor layer to form a second dummy gate; and a fourth step of forming a fifth insulating film around the second dummy gate, etching the fifth insulating film so as to have a sidewall shape to form a sidewall formed of the fifth insulating film, and forming a first epitaxially grown layer on the fin-shaped semiconductor layer.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: February 28, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9576432
    Abstract: A game is executed in a normal round, in a first-type free round, and in a second-type free round. The normal round is executed with a first symbol set including a plurality of symbols. The first-type free round is executed with a second symbol set that includes at least one first symbol in addition to the symbols in the first symbol set. The second-type free round is executed with a third symbol set that includes at least one second symbol in addition to the symbols in the first symbol set, the at least one second symbol being different from the at least one first symbol.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: February 21, 2017
    Assignees: UNIVERSAL ENTERTAINMENT CORPORATION, ARUZA GAMING AMERICA, INC.
    Inventors: Yoichi Kato, Hiroki Nakamura, Masumi Fujisawa, Kazuo Okada
  • Publication number: 20170047428
    Abstract: A method for producing a semiconductor device includes a first step of forming a first insulating film around a fin-shaped semiconductor layer; a second step of forming a first pillar-shaped semiconductor layer, a first dummy gate, a second pillar-shaped semiconductor layer, and a second dummy gate; a third step of forming a third dummy gate and a fourth dummy gate; a fourth step of forming a third diffusion layer in an upper portion of the fin-shaped semiconductor layer, in a lower portion of the first pillar-shaped semiconductor layer, and in a lower portion of the second pillar-shaped semiconductor layer; a fifth step of forming a gate electrode and a gate line around the first pillar-shaped semiconductor layer and forming a contact electrode and a contact line around the second pillar-shaped semiconductor layer; and a sixth step of forming first to fifth contacts.
    Type: Application
    Filed: October 28, 2016
    Publication date: February 16, 2017
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Publication number: 20170047417
    Abstract: A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and a second pillar-shaped semiconductor layer on the fin-shaped semiconductor layer. A metal contact electrode is around the second pillar-shaped semiconductor layer, and a metal contact line is connected to the metal contact electrode. A diffusion layer is in an upper portion of the fin-shaped semiconductor layer, and the contact electrode is connected to the diffusion layer. A contact surrounds an upper sidewall of the second pillar-shaped semiconductor layer and is connected to the contact electrode.
    Type: Application
    Filed: October 28, 2016
    Publication date: February 16, 2017
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Publication number: 20170033108
    Abstract: A semiconductor device includes a first and second fin-shaped semiconductor layers on a substrate. A first insulating film is around the first and second fin-shaped layers. A first and second pillar-shaped semiconductor layers reside on the first and second fin-shaped layers, respectively. A width of a bottom of the first pillar-shaped semiconductor layer is equal to a width of a top of the first fin-shaped semiconductor layer, and a width of a bottom of the second pillar-shaped semiconductor layer is equal to the width of a top of the second fin-shaped semiconductor layer. First and second gate insulating films and first and second metal gate electrodes reside around the first and second pillar-shaped layers, respectively. A metal gate line is connected to the first and second metal gate electrodes and extends in a direction perpendicular to the first and second fin-shaped layers.
    Type: Application
    Filed: September 15, 2016
    Publication date: February 2, 2017
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Publication number: 20170025513
    Abstract: A semiconductor device includes a pillar-shaped semiconductor having an impurity concentration of 1017 cm?3 or less. A first insulator surrounds the pillar-shaped semiconductor and a first metal surrounds a portion of the first insulator at a first end of the pillar-shaped semiconductor. A second metal surrounds a portion of the first insulator at a second end of the pillar-shaped semiconductor, and a third metal surrounds a portion of the first insulator in a region between the first and second metals. The first metal and the second metal are electrically insulated from the third metal. Source/drain regions are defined in the pillar-shaped semiconductor due to a work function difference between the pillar-shaped semiconductor and the first and second metals.
    Type: Application
    Filed: October 6, 2016
    Publication date: January 26, 2017
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Patent number: 9553130
    Abstract: A semiconductor device includes four or more memory cells arranged on a row, the memory cells each including a first pillar-shaped semiconductor layer, a first gate insulating film around the semiconductor layer, a first gate line around the first gate insulating film, a third gate insulating film around an upper portion of the semiconductor layer, a first contact electrode around the third gate insulating film, a second contact electrode connecting upper portions of the semiconductor layer and the first contact electrode, and a magnetic tunnel junction storage element on the second contact electrode, a first source line connecting lower portions of the semiconductor layers to each other, a first bit line extending in a direction perpendicular to a direction of the first gate line and connected to an upper portion of the storage element, and a second source line extending in a direction perpendicular to the first source line.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: January 24, 2017
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20170005264
    Abstract: The present invention provides a memory structure including a resistance-changing storage element, which enables a reset operation with a reset gate and in which cross-sectional areas of a resistance-changing film and a lower electrode in a current-flowing direction can be decreased.
    Type: Application
    Filed: September 14, 2016
    Publication date: January 5, 2017
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Patent number: 9536927
    Abstract: A method for producing a semiconductor device includes forming a fin-shaped semiconductor layer on a semiconductor substrate and a first pillar-shaped semiconductor layer, a first dummy gate layer and a second pillar-shaped semiconductor layer, and a second dummy gate layer. Third and fourth dummy gate layers are formed on sidewalls of the first dummy layer gate, the first pillar-shaped semiconductor layer, the second dummy gate layer and the second pillar-shaped semiconductor layer. An interlayer insulating film is deposited, the dummy gate layers are removed, and a gate insulator is formed film around the first and second pillar-shaped semiconductor layers. A first metal is deposited and a gate electrode and a gate line are formed around the first pillar-shaped semiconductor layer. Second and third metals are deposited and a first contact and a pillar-shaped resistance-changing layer, a lower electrode, and a reset gate are formed.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: January 3, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20160380080
    Abstract: A semiconductor device production method includes a first step of forming a planar silicon layer on a silicon substrate and forming first and second pillar-shaped silicon layers on the planar silicon layer; a second step of forming a gate insulating film around the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, controlling a thickness of the polysilicon film to be smaller than a half of a distance between the first and second pillar-shaped silicon layers, depositing a resist, exposing the polysilicon film on side walls of upper portions of the first and second pillar-shaped semiconductor layers, etching-away the exposed polysilicon film, stripping the third resist, and etching-away the metal film; and a third step of forming a resist for forming a gate line and performing anisotropic etching to form a gate line and first and second gate electrodes.
    Type: Application
    Filed: September 13, 2016
    Publication date: December 29, 2016
    Inventors: Fujio MASUOKA, Nozomu HARADA, Hiroki NAKAMURA, Yisuo LI, Aashit Ramachandra KAMATH, Zhixian CHEN, Teng Soong PHUA, Xinpeng WANG, Patrick Guo-Qiang LO
  • Publication number: 20160380099
    Abstract: A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate formed of a first polysilicon; a third step of forming a second dummy gate on side walls of the first dummy gate and the pillar-shaped semiconductor layer; a fourth step of forming a side wall formed of a fifth insulating film around the second dummy gate, forming a second diffusion layer in an upper portion of the fin-shaped semiconductor layer and a lower portion of the pillar-shaped semiconductor layer, and forming a metal-semiconductor compound on the second diffusion layer; a fifth step of forming a gate electrode and a gate line; and a sixth step of depositing a sixth insulating film, forming a third resist for forming a contact hole on the pillar-shaped semiconductor layer, etching the sixth insulating f
    Type: Application
    Filed: September 13, 2016
    Publication date: December 29, 2016
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Publication number: 20160380116
    Abstract: A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate formed of a first polysilicon; a third step of forming a second dummy gate on side walls of the first dummy gate and the pillar-shaped semiconductor layer; a fourth step of forming a side wall formed of a fifth insulating film around the second dummy gate, forming a second diffusion layer in an upper portion of the fin-shaped semiconductor layer and a lower portion of the pillar-shaped semiconductor layer, and forming a metal-semiconductor compound on the second diffusion layer; a fifth step of forming a gate electrode and a gate line; and a sixth step of depositing a sixth insulating film, forming a third resist for forming a contact hole on the pillar-shaped semiconductor layer, etching the sixth insulating f
    Type: Application
    Filed: September 13, 2016
    Publication date: December 29, 2016
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Patent number: 9530793
    Abstract: A semiconductor device includes a first pillar-shaped semiconductor layer, a first selection gate insulating film, a first selection gate, a first gate insulating film, a first contact electrode, a first bit line connected to an upper portion of the first pillar-shaped semiconductor layer and an upper portion of the first contact electrode, a second pillar-shaped semiconductor layer, a layer including a first charge storage layer, a first control gate, a layer including a second charge storage layer and formed above the first control gate, a second control gate, a second gate insulating film, a second contact electrode having an upper portion connected to an upper portion of the second pillar-shaped semiconductor layer, and a first lower internal line that connects a lower portion of the first pillar-shaped semiconductor layer and a lower portion of the second pillar-shaped semiconductor layer.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: December 27, 2016
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9525038
    Abstract: A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer; and a second step following the first step and including forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to conduct planarization, forming a second resist for forming a gate line and a pillar-shaped semiconductor layer so that the second resist extends in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer and a first dummy gate formed of the first polysilicon.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: December 20, 2016
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20160362761
    Abstract: A steel sheet for crown caps includes C: 0.0005 to 0.0050%, Si: 0.020% or less, Mn: 0.10 to 0.60%, P: 0.020% or less, S: 0.020% or less, Al: 0.01 to 0.10%, N: 0.0050% or less, Nb: 0.010 to 0.050%, and Fe and inevitable impurities. The steel sheet has an average r value of 1.30 or more and a YP of 450 MPa or more and 650 MPa or less. The steel sheet is obtained by hot rolling a steel slab at a slab reheating temperature of 1,150° C. or higher and a finishing temperature of 870° C. or higher; coiling the hot rolled steel sheet at a coiling temperature of 600° C. or higher, performing pickling; then-performing primary cold rolling; performing annealing at an annealing temperature of recrystallization temperature or more and 790° ° C. or less; and performing secondary cold rolling at a rolling reduction of 10% or more and 50% or less.
    Type: Application
    Filed: February 13, 2015
    Publication date: December 15, 2016
    Applicant: JFE STEEL CORPORATION
    Inventors: Tomonari HIRAGUCHI, Katsumi KOJIMA, Hiroki NAKAMURA, Masami TSUJIMOTO, Toshihiro KIKUCHI
  • Publication number: 20160365511
    Abstract: A method for producing a device includes depositing a lower electrode metal and a film whose resistance changes. The film whose resistance changes and the lower electrode metal are etched to form a pillar-shaped phase-change layer and a lower electrode. A reset gate insulating film and a reset gate metal are deposited and etched to form reset gates.
    Type: Application
    Filed: August 26, 2016
    Publication date: December 15, 2016
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Patent number: 9520473
    Abstract: A method for producing a semiconductor device includes a first step of forming a first insulating film around a fin-shaped semiconductor layer; a second step of forming a first pillar-shaped semiconductor layer, a first dummy gate, a second pillar-shaped semiconductor layer, and a second dummy gate; a third step of forming a third dummy gate and a fourth dummy gate; a fourth step of forming a third diffusion layer in an upper portion of the fin-shaped semiconductor layer, in a lower portion of the first pillar-shaped semiconductor layer, and in a lower portion of the second pillar-shaped semiconductor layer; a fifth step of forming a gate electrode and a gate line around the first pillar-shaped semiconductor layer and forming a contact electrode and a contact line around the second pillar-shaped semiconductor layer; and a sixth step of forming first to fifth contacts.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: December 13, 2016
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20160359106
    Abstract: A semiconductor device includes four or more memory cells arranged on a row, the memory cells each including a first pillar-shaped semiconductor layer, a first gate insulating film around the semiconductor layer, a first gate line around the first gate insulating film, a third gate insulating film around an upper portion of the semiconductor layer, a first contact electrode around the third gate insulating film, a second contact electrode connecting upper portions of the semiconductor layer and the first contact electrode, and a magnetic tunnel junction storage element on the second contact electrode, a first source line connecting lower portions of the semiconductor layers to each other, a first bit line extending in a direction perpendicular to a direction of the first gate line and connected to an upper portion of the storage element, and a second source line extending in a direction perpendicular to the first source line.
    Type: Application
    Filed: August 16, 2016
    Publication date: December 8, 2016
    Inventors: FUJIO MASUOKA, HIROKI NAKAMURA
  • Publication number: 20160343854
    Abstract: A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate. A first insulating film is around the fin-shaped semiconductor layer and a pillar-shaped semiconductor layer is on the fin-shaped semiconductor layer. A gate insulating film is around the pillar-shaped semiconductor layer. A metal gate electrode is around the gate insulating film and a metal gate line is connected to the metal gate electrode. A metal gate pad is connected to the metal gate line, and a width of the metal gate electrode and a width of the metal gate pad is larger than a width of the metal gate line.
    Type: Application
    Filed: August 8, 2016
    Publication date: November 24, 2016
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Publication number: 20160343879
    Abstract: A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate; a third step of forming a second dummy gate on side walls of the first dummy gate and the pillar-shaped semiconductor layer; a fourth step of forming a fifth insulating film and a sixth insulating film around the second dummy gate; a fifth step of depositing a first interlayer insulating film, removing the second dummy gate and the first dummy gate, forming a gate insulating film around the pillar-shaped semiconductor layer, depositing metal, and performing etch back to form a gate electrode and a gate line; and a sixth step of forming a first diffusion layer in an upper portion of the pillar-shaped semiconductor layer.
    Type: Application
    Filed: August 4, 2016
    Publication date: November 24, 2016
    Inventors: FUJIO MASUOKA, HIROKI NAKAMURA