Patents by Inventor Hiroki Nakamura

Hiroki Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9640637
    Abstract: A method for producing a semiconductor device includes a first step of forming a first insulating film around a fin-shaped semiconductor layer; a second step of forming a first pillar-shaped semiconductor layer, a first dummy gate, a second pillar-shaped semiconductor layer, and a second dummy gate; a third step of forming a third dummy gate and a fourth dummy gate; a fourth step of forming a third diffusion layer in an upper portion of the fin-shaped semiconductor layer, in a lower portion of the first pillar-shaped semiconductor layer, and in a lower portion of the second pillar-shaped semiconductor layer; a fifth step of forming a gate electrode and a gate line around the first pillar-shaped semiconductor layer and forming a contact electrode and a contact line around the second pillar-shaped semiconductor layer; and a sixth step of forming first to fifth contacts.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: May 2, 2017
    Assignee: UNISANTIS ELECTRONICS SIGNAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9640628
    Abstract: An SGT production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask formed from a third insulating film; a third step of forming a second hard mask on a side wall of the first hard mask, and forming a second dummy gate; a fourth step of forming a sidewall and forming a second diffusion layer; a fifth step of depositing an interlayer insulating film, exposing upper portions of the second dummy gate and the first dummy gate, removing the second dummy gate and the first dummy gate, forming a first gate insulating film, and forming a gate electrode and a gate line; and a sixth step of forming a first contact and a second contact.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: May 2, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9634249
    Abstract: A device includes a pillar-shaped insulating layer above a first pillar-shaped semiconductor layer. A resistance-changing film is around an upper portion of the pillar-shaped insulating layer and a lower electrode is around a lower portion of the pillar-shaped insulating layer and connected to the resistance-changing film. A reset gate insulating film surrounds the resistance-changing film, and a reset gate surrounds the reset gate insulating film.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: April 25, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20170110510
    Abstract: A semiconductor device includes four or more first memory cells arranged on a row, the first memory cells each including a first pillar-shaped semiconductor layer, a first gate insulating film formed around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film, and a first magnetic tunnel junction storage element formed on the first pillar-shaped semiconductor layer. The semiconductor device further includes a first source line that connects lower portions of the first pillar-shaped semiconductor layers to each other, a first bit line that extends in a direction perpendicular to a direction in which the first gate line extends and that is connected to an upper portion of the first magnetic tunnel junction storage element, and a second source line that extends in a direction perpendicular to a direction in which the first source line extends.
    Type: Application
    Filed: December 28, 2016
    Publication date: April 20, 2017
    Inventors: FUJIO MASUOKA, HIROKI NAKAMURA
  • Patent number: 9627495
    Abstract: A method of fabricating a semiconductor device includes forming fin-shaped semiconductor layers on a semiconductor substrate. First and second pillar-shaped semiconductor layers are formed, and first and second control gates are formed around the first and second pillar-shaped semiconductor layers, respectively. First and second selection gates are formed around the first and second pillar-shaped semiconductor layers, respectively. First and second contact electrodes are formed around upper portions of the first and second pillar-shaped semiconductor layers, respectively.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: April 18, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9620564
    Abstract: A semiconductor device includes four or more first memory cells arranged on a row, the first memory cells each including a first pillar-shaped semiconductor layer, a first gate insulating film formed around the first pillar-shaped semiconductor layer, a first gate line formed around the first gate insulating film, and a first magnetic tunnel junction storage element formed on the first pillar-shaped semiconductor layer. The semiconductor device further includes a first source line that connects lower portions of the first pillar-shaped semiconductor layers to each other, a first bit line that extends in a direction perpendicular to a direction in which the first gate line extends and that is connected to an upper portion of the first magnetic tunnel junction storage element, and a second source line that extends in a direction perpendicular to a direction in which the first source line extends.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: April 11, 2017
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9614075
    Abstract: A semiconductor device includes a fin-shaped silicon layer on a silicon substrate, and a first insulating film around the fin-shaped silicon layer. A pillar-shaped silicon layer is on the fin-shaped silicon layer, where a pillar diameter of the pillar-shaped silicon layer is equal to a fin width of the fin-shaped silicon layer, and where the pillar diameter and the fin width parallel to the surface. A first diffusion layer is in an upper portion of the fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer, and a second diffusion layer is in an upper portion of the pillar-shaped silicon layer. A gate insulating film is around the pillar-shaped silicon layer and a metal gate electrode is around the gate insulating film. A metal gate wiring is connected to the metal gate electrode and a contact is on the second diffusion layer.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: April 4, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9601505
    Abstract: A semiconductor device includes a first selection gate insulating film surrounding a first pillar-shaped semiconductor layer, a first selection gate surrounding the first selection gate insulating film, a first bit line connected to the first pillar-shaped semiconductor layer, a layer including a first charge storage layer which surrounds a second pillar-shaped semiconductor layer, a first control gate surrounding the layer, a layer including a second charge storage layer which surrounds the second pillar-shaped semiconductor layer, a second control gate surrounding the layer, a first lower-portion internal line connecting the first and second pillar-shaped semiconductor layers, a layer including a third charge storage layer, a third control gate, a layer including a fourth charge storage layer, a fourth control gate, a second selection gate insulating film, a second selection gate, a first source line, and a second lower-portion internal line.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: March 21, 2017
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9601618
    Abstract: A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and that extends in a first direction with a first insulating film around the fin-shaped semiconductor layer. A pillar-shaped semiconductor layer resides on the fin-shaped semiconductor layer. A width of the bottom of the pillar-shaped semiconductor layer is equal to a width of the top of the fin-shaped semiconductor layer. A gate insulating film is around the pillar-shaped semiconductor layer and a metal gate electrode is around the gate insulating film. A metal gate line is connected to the metal gate electrode, and a nitride film is on an entire top surface of the metal gate electrode and the metal gate line, except at a bottom of a contact.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: March 21, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20170077315
    Abstract: A semiconductor device includes a first pillar-shaped semiconductor layer, a first selection gate insulating film, a first selection gate, a first gate insulating film, a first contact electrode, a first bit line connected to an upper portion of the first pillar-shaped semiconductor layer and an upper portion of the first contact electrode, a second pillar-shaped semiconductor layer, a layer including a first charge storage layer, a first control gate, a layer including a second charge storage layer and formed above the first control gate, a second control gate, a second gate insulating film, a second contact electrode having an upper portion connected to an upper portion of the second pillar-shaped semiconductor layer, and a first lower internal line that connects a lower portion of the first pillar-shaped semiconductor layer and a lower portion of the second pillar-shaped semiconductor layer.
    Type: Application
    Filed: November 3, 2016
    Publication date: March 16, 2017
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Publication number: 20170077267
    Abstract: A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer; and a second step following the first step and including forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to conduct planarization, forming a second resist for forming a gate line and a pillar-shaped semiconductor layer so that the second resist extends in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer and a first dummy gate formed of the first polysilicon.
    Type: Application
    Filed: November 3, 2016
    Publication date: March 16, 2017
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Publication number: 20170077265
    Abstract: A semiconductor device includes a fin-shaped semiconductor layer and a pillar-shaped semiconductor layer on the fin-shaped semiconductor layer. A metal gate line is connected to a metal gate electrode and extends in a direction perpendicular to a direction that of the fin-shaped semiconductor layer. A width of a bottom of the pillar-shaped semiconductor layer in a direction parallel to a direction in which the metal gate line extends is equal to a width of a top of the fin-shaped semiconductor layer in the direction parallel to the direction of the metal gate line. A gate insulating film is in contact with an underside of the gate electrode and the gate line and separates the metal gate electrode and the metal gate line from the fin-shaped semiconductor layer and a first insulating film. An outer width of the metal gate electrode is equal to a width of the metal gate line.
    Type: Application
    Filed: November 3, 2016
    Publication date: March 16, 2017
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Patent number: 9595476
    Abstract: A semiconductor device includes first and second fin-shaped semiconductor layers on a substrate. First and second pillar-shaped semiconductor layers reside on the first and second fin-shaped semiconductor layers, respectively, where a width of the bottom of the first and second pillar-shaped semiconductors is equal to a width of the top of the first and second fin-shaped semiconductor layers, respectively. A gate insulating film and metal gate electrode are around underlying gate insulating layers on each fin-shaped semiconductor layer. A metal gate line is connected to the metal gate electrodes and extends in a direction perpendicular to the first and second fin-shaped semiconductor layers. Contacts reside on the upper portion of diffusion layers in upper portions of the first and second pillar-shaped semiconductor layers and are directly connected to the diffusion layers.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: March 14, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9589425
    Abstract: Provided is a slot machine capable of reducing unfairness which may result between a player who has made an investment and a player who has not made an investment and allowing a player to proceed with a game by making an investment in expectation of a jackpot at ease. Each money amount which is constant is accumulated independently of a number of bets each time betting is conducted, and upon winning a jackpot, a money amount calculated by multiplying a money amount accumulated until then by a multiplying factor based on the number of bets is provided.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: March 7, 2017
    Assignees: UNIVERSAL ENTERTAINMENT CORPORATION, ARUZE GAMING AMERICA, INC.
    Inventors: Yoichi Kato, Hiroaki Kashima, Naoya Shirai, Masumi Fujisawa, Hiroki Nakamura, Takeshi Aoki, Kazuo Okada
  • Patent number: 9590098
    Abstract: A method for producing a semiconductor device includes a first step of forming a first insulating film around the fin-shaped semiconductor layer; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate formed of a first polysilicon; a third step of forming a second dummy gate on sidewalls of the first dummy gate and the pillar-shaped semiconductor layer; a fourth step of forming a fifth insulating film left as a sidewall around the second dummy gate, forming a second diffusion layer in an upper portion of the fin-shaped semiconductor layer and a lower portion of the pillar-shaped semiconductor layer, and forming a metal-semiconductor compound on the second diffusion layer; a fifth step of forming a gate electrode and a gate line; and a sixth step of depositing a second gate insulating film around the pillar-shaped semiconductor layer and on the gate electrode and the gate line, removing a portion of the second gate insulating film on the gate line, depositing a second metal, etchin
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: March 7, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE, LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9590011
    Abstract: A semiconductor device includes a pillar-shaped resistance-changing layer and a reset gate insulating film that surrounds the pillar-shaped resistance-changing layer. A reset gate surrounds the reset gate insulating film, and the reset gate is electrically insulated from the pillar-shaped resistance-changing layer.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: March 7, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9590175
    Abstract: A semiconductor device includes four or more memory cells arranged on a row, the memory cells each including a first pillar-shaped semiconductor layer, a first gate insulating film around the semiconductor layer, a first gate line around the first gate insulating film, a third gate insulating film around an upper portion of the semiconductor layer, a first contact electrode around the third gate insulating film, a second contact electrode connecting upper portions of the semiconductor layer and the first contact electrode, and a magnetic tunnel junction storage element on the second contact electrode, a first source line connecting lower portions of the semiconductor layers to each other, a first bit line extending in a direction perpendicular to a direction of the first gate line and connected to an upper portion of the storage element, and a second source line extending in a direction perpendicular to the first source line.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: March 7, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9583630
    Abstract: A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate, and forming a first insulating film; a second step of forming a second insulating film, and forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; a third step of forming a second hard mask on a side wall of the first hard mask, and etching a second polysilicon so as to be left on side walls of the first dummy gate and the pillar-shaped semiconductor layer to form a second dummy gate; and a fourth step of forming a fifth insulating film around the second dummy gate, etching the fifth insulating film so as to have a sidewall shape to form a sidewall formed of the fifth insulating film, and forming a first epitaxially grown layer on the fin-shaped semiconductor layer.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: February 28, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9576432
    Abstract: A game is executed in a normal round, in a first-type free round, and in a second-type free round. The normal round is executed with a first symbol set including a plurality of symbols. The first-type free round is executed with a second symbol set that includes at least one first symbol in addition to the symbols in the first symbol set. The second-type free round is executed with a third symbol set that includes at least one second symbol in addition to the symbols in the first symbol set, the at least one second symbol being different from the at least one first symbol.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: February 21, 2017
    Assignees: UNIVERSAL ENTERTAINMENT CORPORATION, ARUZA GAMING AMERICA, INC.
    Inventors: Yoichi Kato, Hiroki Nakamura, Masumi Fujisawa, Kazuo Okada
  • Publication number: 20170047428
    Abstract: A method for producing a semiconductor device includes a first step of forming a first insulating film around a fin-shaped semiconductor layer; a second step of forming a first pillar-shaped semiconductor layer, a first dummy gate, a second pillar-shaped semiconductor layer, and a second dummy gate; a third step of forming a third dummy gate and a fourth dummy gate; a fourth step of forming a third diffusion layer in an upper portion of the fin-shaped semiconductor layer, in a lower portion of the first pillar-shaped semiconductor layer, and in a lower portion of the second pillar-shaped semiconductor layer; a fifth step of forming a gate electrode and a gate line around the first pillar-shaped semiconductor layer and forming a contact electrode and a contact line around the second pillar-shaped semiconductor layer; and a sixth step of forming first to fifth contacts.
    Type: Application
    Filed: October 28, 2016
    Publication date: February 16, 2017
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA