Patents by Inventor Hiroki TOKUHIRA
Hiroki TOKUHIRA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210202838Abstract: A resistance variable device of an embodiment includes a stack arranged between a first electrode and a second electrode and including a resistance variable layer and a chalcogen-containing layer. The chalcogen-containing layer contains a material having a composition represented by a general formula: C1xC2yAz, where C1 is at least one element selected from Sc, Y, Zr, and Hf, C2 is at least one element selected from C, Si, Ge, B, Al, Ga, and In, A is at least one element selected from S, Se, and Te, and x, y, and z are numbers representing atomic ratios satisfying 0<x<1, 0<y<1, 0<z<1, and x+y+z=1, and when an oxidation number of the element C1 is set to a, and an oxidation number of the element C2 is set to b, the atomic ratio x of the element C2 satisfies x?(3?(3+b)×y?z)/(3+a).Type: ApplicationFiled: September 8, 2020Publication date: July 1, 2021Applicant: Kioxia CorporationInventors: Hiroki KAWAI, Katsuyoshi KOMATSU, Tadaomi DAIBOU, Hiroki TOKUHIRA, Masatoshi YOSHIKAWA, Yuichi ITO
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Patent number: 10930660Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: GrantFiled: February 18, 2020Date of Patent: February 23, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
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Publication number: 20210005616Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: ApplicationFiled: September 22, 2020Publication date: January 7, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hiroki TOKUHIRA, Takahisa KANEMURA, Shigeo KONDO, Michiru HOGYOKU
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Patent number: 10872900Abstract: An example semiconductor device includes: n conductive layers including first to nth conductive layers stacked in a first direction; a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type closer to the nth conductive layer than the first semiconductor region; a semiconductor layer provided between the first semiconductor region and the second semiconductor region, extending in the first direction, penetrating the n conductive layers, and having an impurity concentration lower than a first conductive impurity concentration of the first region and a second conductive impurity concentration of the second region; n charge storage regions including first to nth charge storage regions provided between the n conductive layers and the semiconductor layer, and a control circuit that controls a voltage applied to the n conductive layers to always prevent charges from being stored in at least one of the n charge storage regions.Type: GrantFiled: February 22, 2019Date of Patent: December 22, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tomoya Sanuki, Yusuke Higashi, Hideto Horii, Masaki Kondo, Hiroki Tokuhira, Hideaki Aochi
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Patent number: 10847223Abstract: A storage device includes a first group of wirings extending in a first direction, a second group of wirings extending in a second direction, and memory cells between the first and second groups, each including a variable resistance element and a selection element becoming conductive when a voltage greater than a threshold is applied. Va applied across a first cell to be selected satisfies Va>Vd>Vb and Va>Vd>Vc. A first wiring of the first group and a second wiring of the second group are connected to the first cell. A third wiring of the first group and a fourth wiring of the second group are adjacent to the first wiring and the second wiring. Vb, Vc, and Vd are applied across a second cell between the first and fourth wirings, a third cell between the second and third wirings, and a fourth cell between the third and fourth wirings.Type: GrantFiled: August 30, 2019Date of Patent: November 24, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Naoki Kusunoki, Toshiyuki Enda, Hiroki Tokuhira, Takayuki Miyazaki
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Publication number: 20200294590Abstract: A storage device includes a first group of wirings extending in a first direction, a second group of wirings extending in a second direction, and memory cells between the first and second groups, each including a variable resistance element and a selection element becoming conductive when a voltage greater than a threshold is applied. Va applied across a first cell to be selected satisfies Va>Vd>Vb and Va>Vd>Vc. A first wiring of the first group and a second wiring of the second group are connected to the first cell. A third wiring of the first group and a fourth wiring of the second group are adjacent to the first wiring and the second wiring. Vb, Vc, and Vd are applied across a second cell between the first and fourth wirings, a third cell between the second and third wirings, and a fourth cell between the third and fourth wirings.Type: ApplicationFiled: August 30, 2019Publication date: September 17, 2020Inventors: Naoki KUSUNOKI, Toshiyuki ENDA, Hiroki TOKUHIRA, Takayuki MIYAZAKI
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Publication number: 20200185395Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: ApplicationFiled: February 18, 2020Publication date: June 11, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hiroki TOKUHIRA, Takahisa KANEMURA, Shigeo KONDO, Michiru HOGYOKU
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Patent number: 10672793Abstract: A semiconductor memory device includes a stacked body including insulating layers and gate electrode layers alternately stacked in a direction, a semiconductor layer extending in the direction, and a gate insulating layer provided between the semiconductor layer and the gate electrode layer, and including a first layer, a second layer, and a third layer between the first layer and the second layer. The first layer includes a first insulator, the second layer includes at least one oxide selected from aluminum oxide, yttrium oxide, lanthanum oxide, gadolinium oxide, ytterbium oxide, hafnium oxide, and zirconium oxide, the third layer includes at least one material selected from silicon, germanium, silicon germanium and silicon carbide, and the third layer is positioned between the semiconductor layer and the insulating layer.Type: GrantFiled: February 5, 2019Date of Patent: June 2, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroki Tokuhira, Kazuhiko Yamamoto, Kunifumi Suzuki
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Patent number: 10608007Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: GrantFiled: July 15, 2019Date of Patent: March 31, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
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Publication number: 20200091171Abstract: A semiconductor memory device includes a stacked body including insulating layers and gate electrode layers alternately stacked in a direction, a semiconductor layer extending in the direction, and a gate insulating layer provided between the semiconductor layer and the gate electrode layer, and including a first layer, a second layer, and a third layer between the first layer and the second layer. The first layer includes a first insulator, the second layer includes at least one oxide selected from aluminum oxide, yttrium oxide, lanthanum oxide, gadolinium oxide, ytterbium oxide, hafnium oxide, and zirconium oxide, the third layer includes at least one material selected from silicon, germanium, silicon germanium and silicon carbide, and the third layer is positioned between the semiconductor layer and the insulating layer.Type: ApplicationFiled: February 5, 2019Publication date: March 19, 2020Applicant: Toshiba Memory CorporationInventors: Hiroki TOKUHIRA, Kazuhiko YAMAMOTO, Kunifumi SUZUKI
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Publication number: 20200091174Abstract: An example semiconductor device includes: n conductive layers including first to nth conductive layers stacked in a first direction; a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type closer to the nth conductive layer than the first semiconductor region; a semiconductor layer provided between the first semiconductor region and the second semiconductor region, extending in the first direction, penetrating the n conductive layers, and having an impurity concentration lower than a first conductive impurity concentration of the first region and a second conductive impurity concentration of the second region; n charge storage regions including first to nth charge storage regions provided between the n conductive layers and the semiconductor layer, and a control circuit that controls a voltage applied to the n conductive layers to always prevent charges from being stored in at least one of the n charge storage regions.Type: ApplicationFiled: February 22, 2019Publication date: March 19, 2020Applicant: Toshiba Memory CorporationInventors: Tomoya SANUKI, Yusuke HIGASHI, Hideto HORII, Masaki KONDO, Hiroki TOKUHIRA, Hideaki AOCHI
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Publication number: 20190341391Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: ApplicationFiled: July 15, 2019Publication date: November 7, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hiroki TOKUHIRA, Takahisa KANEMURA, Shigeo KONDO, Michiru HOGYOKU
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Patent number: 10431590Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: GrantFiled: January 5, 2018Date of Patent: October 1, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
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Publication number: 20190013355Abstract: According to one embodiment, the first lines extend in a first direction. The first gate electrodes extend in a second direction intersecting with the first direction. The second lines extend in a third direction orthogonal to the first direction and the second direction. The semiconductor portion is disposed between the first gate electrodes, and between one of the first lines and one of the second lines, and connected to the first line and the second line. The semiconductor portion has a column shape. The semiconductor portion includes a plurality of channels isolated in a direction orthogonal to the third direction. The second gate electrode is provided between the channels. The insulating film is provided between the semiconductor portion and the first gate electrode, and between the semiconductor portion and the second gate electrode.Type: ApplicationFiled: February 27, 2018Publication date: January 10, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hikari TAJIMA, Takashi IZUMIDA, Takahisa KANEMURA, Hiroki TOKUHIRA
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Patent number: 9985044Abstract: A semiconductor memory device according to an embodiment, includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: GrantFiled: September 14, 2016Date of Patent: May 29, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroki Tokuhira, Takahisa Kanemura, Shigeo Kondo, Michiru Hogyoku
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Publication number: 20180130810Abstract: A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: ApplicationFiled: January 5, 2018Publication date: May 10, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hiroki TOKUHIRA, Takahisa KANEMURA, Shigeo KONDO, Michiru HOGYOKU
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Publication number: 20170263614Abstract: A semiconductor memory device according to an embodiment, includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.Type: ApplicationFiled: September 14, 2016Publication date: September 14, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: HIROKI TOKUHIRA, TAKAHISA KANEMURA, SHIGEO KONDO, MICHIRU HOGYOKU
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Publication number: 20170084329Abstract: According to an embodiment, a semiconductor memory device comprises: a first wiring line; a memory string connected to this first wiring line; and a plurality of second wiring lines connected to this memory string. In addition, this memory string comprises: a first semiconductor layer connected to the first wiring line; a plurality of second semiconductor layers connected to this first semiconductor layer; and a variable resistance element connected between this second semiconductor layer and the second wiring line. Moreover, of the first semiconductor layer and the plurality of second semiconductor layers, one includes a semiconductor of a first conductivity type, and the other includes a semiconductor of a second conductivity type.Type: ApplicationFiled: March 15, 2016Publication date: March 23, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Hiroki TOKUHIRA, Hiroyoshi TANIMOTO, Takashi IZUMIDA
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Patent number: 9595324Abstract: According to an embodiment, a semiconductor memory device comprises: a first wiring line; a memory string connected to this first wiring line; and a plurality of second wiring lines connected to this memory string. In addition, this memory string comprises: a first semiconductor layer connected to the first wiring line; a plurality of second semiconductor layers connected to this first semiconductor layer; and a variable resistance element connected between this second semiconductor layer and the second wiring line. Moreover, of the first semiconductor layer and the plurality of second semiconductor layers, one includes a semiconductor of a first conductivity type, and the other includes a semiconductor of a second conductivity type.Type: GrantFiled: March 15, 2016Date of Patent: March 14, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hiroki Tokuhira, Hiroyoshi Tanimoto, Takashi Izumida
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Patent number: 9536894Abstract: According to an embodiment, a non-volatile memory device includes first electrodes arranged in a first direction, a second electrode disposed on a side of the first electrodes in the first direction, a semiconductor layer extending in the first direction through the first electrodes and the second electrode, and a memory film provided between the semiconductor layer and each of the first electrodes. The semiconductor layer includes crystal grains and has a first portion and a second portion, the first portion being adjacent to the first electrodes, and the second portion being adjacent to at least a part of the second electrode, wherein the first portion includes a larger crystal grain than a crystal grain in the second portion.Type: GrantFiled: February 11, 2015Date of Patent: January 3, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Hikari Tajima, Masaki Kondo, Tsukasa Nakai, Takashi Izumida, Hiroki Tokuhira