Abstract: An integrated circuit device according to an embodiment includes a semiconductor substrate, a first semiconductor member and a second semiconductor member provided on the semiconductor substrate, a first electrode disposed between the first semiconductor member and the second semiconductor member, and a second electrode disposed between the semiconductor substrate and the first electrode. The first semiconductor member and the second semiconductor member extend in a first direction perpendicular to an upper surface of the semiconductor substrate. The first semiconductor member and the second semiconductor member are separated in a second direction orthogonal to the first direction. The first electrode extends in a third direction intersecting both the first direction and the second direction. The second electrode extends in the third direction.

Abstract: A memory device according to an embodiment includes a memory element; and a transistor including a semiconductor layer and a plurality of gates, wherein the plurality of gates include: a first set of gates, the gates being disposed in a manner to sandwich the semiconductor layer, and a second set of gates, the gates being disposed in a manner to sandwich the semiconductor layer, the gates included in the first set is disposed in a manner to separate from the gates included in the second set in a direction along a side surface of the semiconductor layer.

Abstract: According to an embodiment, a non-volatile memory device includes first electrodes arranged in a first direction, a second electrode disposed on a side of the first electrodes in the first direction, a semiconductor layer extending in the first direction through the first electrodes and the second electrode, and a memory film provided between the semiconductor layer and each of the first electrodes. The semiconductor layer includes crystal grains and has a first portion and a second portion, the first portion being adjacent to the first electrodes, and the second portion being adjacent to at least a part of the second electrode, wherein the first portion includes a larger crystal grain than a crystal grain in the second portion.

Abstract: According to an embodiment, a simulation method for resistance variations of a plurality of wires includes creating a numerical expression model for the resistance that is a function of parameters of a cross-sectional shape of the wire, based on the resistance calculated in a Monte Carlo Simulation, dividing each of the wires into a plurality of small elements in a length direction, calculating the resistance of each of the small elements by assigning the parameters of the cross-sectional shape characterizing the cross-sectional shape of each of the small elements to the numerical expression model, and calculating a sum of the resistances of the small elements in each of the wires.

Abstract: An integrated circuit device according to an embodiment, includes a semiconductor member, a first electrode and a second electrode. The semiconductor member includes a first portion of a first conductivity type, a second portion of a second conductivity type, and a third portion of the first conductivity type disposed in this order along a first direction. The first electrode is disposed on a second direction side as viewed from the semiconductor member. The second electrode is disposed on an opposite side of the second direction as viewed from the semiconductor member. An end portion of the second electrode on a first direction side is located in the first direction side rather than that of the first electrode. An end portion of the second electrode on an opposite side of the first direction is located in the first direction side rather than that of the first electrode.

Abstract: An integrated circuit device according to an embodiment includes a semiconductor substrate, a first semiconductor member and a second semiconductor member provided on the semiconductor substrate, a first electrode disposed between the first semiconductor member and the second semiconductor member, and a second electrode disposed between the semiconductor substrate and the first electrode. The first semiconductor member and the second semiconductor member extend in a first direction perpendicular to an upper surface of the semiconductor substrate. The first semiconductor member and the second semiconductor member are separated in a second direction orthogonal to the first direction. The first electrode extends in a third direction intersecting both the first direction and the second direction. The second electrode extends in the third direction.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises memory cells each which stores data with two or more levels. Each of the memory cells includes a semiconductor layer, a first insulating layer on the semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer, and the second insulating layer includes a ferroelectric layer.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises memory cells each which stores data with two or more levels. Each of the memory cells includes a semiconductor layer, a first insulating layer on the semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer, and the second insulating layer includes a ferroelectric layer.