Patents by Inventor Hiroko Nakamura

Hiroko Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090246891
    Abstract: A mark forming method includes forming a first mask layer on a semiconductor substrate; forming at least three first patterns having periodicity on the first mask layer; forming a second mask layer on the first mask layer having the first patterns formed thereon; and forming an opening in the second mask layer to cover at least two patterns on ends of the at least three first patterns, thereby forming a mark composed of exposed ones of the first patterns.
    Type: Application
    Filed: March 20, 2009
    Publication date: October 1, 2009
    Inventors: Takashi Sato, Hiroko Nakamura, Masaru Suzuki, Ryoichi Inanami
  • Publication number: 20090233955
    Abstract: Derivatives of pyrrolo[2,3-b]pyridine which are useful as SGK-1 kinase inhibitors are described herein. The invention described herein also describes pharmaceutical compositions containing derivatives of pyrrolo[2,3-b]pyridine and methods of using pyrrolo[2,3-b]pyridine derivatives and pharmaceutical compositions thereof in the treatment of diseases mediated by SGK-1.
    Type: Application
    Filed: December 8, 2005
    Publication date: September 17, 2009
    Inventors: James S. Frazee, Marlys Hammond, Sharada Manns, Scott Kevin Thompson, David G. Washburn, Kazuya Kano, Hiroko Nakamura
  • Patent number: 7560197
    Abstract: A mask pattern data producing method is disclosed, which comprises preparing design pattern data in which contact holes are arranged on part of the grid points in matrix, preparing first mask pattern data in which first opening patterns are arranged on all of the grid points, and designing second mask pattern data in which second opening patterns and third opening patterns are arranged, the second opening patterns being arranged on the grid points at which the contact holes are arranged in the design pattern data to include the first opening patterns, the third opening patterns being arranged on a pair of grid points, which is a pair of diagonal grid points only on which the contact holes are arranged in a unit grid formed by four grid points, to include the first opening patterns arranged on the pair of grid points, in place of the second opening patterns.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: July 14, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroko Nakamura, Toshiya Kotani, Satoshi Tanaka, Shoji Mimotogi
  • Publication number: 20090011370
    Abstract: A pattern forming method using two layers of resist pattern stacked one on the other has been disclosed. First, a first resist pattern is formed on a to-be-processed film. The first resist pattern is slimmed. On the slimmed first resist pattern and to-be-processed film, a second resist pattern is formed. With the first and second resist patterns as a mask, the film is processed.
    Type: Application
    Filed: June 10, 2008
    Publication date: January 8, 2009
    Inventors: Hiroko Nakamura, Koji Hashimoto, Soichi Inoue, Toshiya Kotani
  • Publication number: 20080305443
    Abstract: A resist pattern is formed on a to-be-processed film. Ions are implanted in the upper surface of the resist pattern. After ion implantation, an organic film is formed to cover the resist pattern and heated. A crosslinked resin film made of the organic film which has crosslinked is formed on the sidewall of the resist pattern by developing the organic film after heating. After formation of the crosslinked resin film, the resist pattern is removed. The to-be-processed film is processed using the crosslinked resin film as a mask.
    Type: Application
    Filed: June 9, 2008
    Publication date: December 11, 2008
    Inventor: Hiroko NAKAMURA
  • Publication number: 20080197456
    Abstract: A substrate polishing method, a semiconductor device and a fabrication method for a semiconductor device are disclosed by which high planarization polishing can be achieved. In the substrate polishing method, two or more different slurries formed from ceria abrasive grains having different BET values from each other are used to carry out two or more stages of chemical-mechanical polishing processing of a polishing object oxide film on a substrate to flatten the polishing object film.
    Type: Application
    Filed: January 3, 2008
    Publication date: August 21, 2008
    Applicant: Sony Corporation
    Inventors: Hiroko Nakamura, Takaaki Kozuki, Takayuki Enomoto, Yuichi Yamamoto
  • Publication number: 20080070402
    Abstract: A block film is formed on a region which includes a region of an insulating layer where a first hole is to be formed, and in which no second hole is to be formed, and a resist film having openings for forming the first and second holes is formed on the block film and insulating layer. Etching is performed by using the resist film as a mask, thereby forming the first hole in the block film and insulating layer, and the second hole in the insulating layer. The depth of the first hole from the upper surface of the insulating layer is smaller than that of the second hole, so the first hole does not reach the semiconductor substrate.
    Type: Application
    Filed: September 18, 2007
    Publication date: March 20, 2008
    Inventors: Toshiya Kotani, Hiroko Nakamura, Koji Hashimoto
  • Patent number: 7319944
    Abstract: A computer implemented method for development profile simulation in accordance with an embodiment of the present invention includes calculating optical intensities in a photosensitive resist, calculating a spatial average value of the optical intensities, reading a measured changing ratio of a dissolution rate of the photosensitive resist relating to an alkaline concentration changed by at least one of exposure dose on the photosensitive resist, a position in the thickness direction of the photosensitive resist and an alkaline concentration of developer for the photosensitive resist, obtaining a calculated dissolution rate by using the spatial average value and the measured changing ratio, and predicting a pattern shape of the photosensitive resist from the calculated dissolution rate.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: January 15, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroko Nakamura, Shoji Mimotogi, Yasunobu Onishi
  • Publication number: 20070269746
    Abstract: A method of forming a pattern on a photosensitive resin film in lithography, a method of forming a pattern for a semiconductor device, and a method of manufacturing a semiconductor device using the patterned film are disclosed. In an aspect of the invention, there is provided a method of forming a pattern on a photosensitive resin film, comprising forming a processing-object film above a semiconductor substrate, forming a first patterned photosensitive resin layer on the processing-object film, implanting ions into the first patterned photosensitive resin layer, the sum (Rp+3dRp) of a projected range (Rp) for the ions in the first photosensitive resin layer and three times a standard deviation (dRp) of the projected range being greater than a thickness of the first patterned photosensitive resin layer, and forming a second patterned photosensitive resin layer on the ion-implanted first patterned photosensitive resin layer.
    Type: Application
    Filed: May 16, 2007
    Publication date: November 22, 2007
    Inventor: Hiroko Nakamura
  • Publication number: 20070218673
    Abstract: A manufacturing method of a semiconductor device including a pattern forming method, a reticle correcting method, and a reticle pattern data correcting method are disclosed.
    Type: Application
    Filed: March 13, 2007
    Publication date: September 20, 2007
    Inventor: Hiroko Nakamura
  • Patent number: 7151953
    Abstract: A communication apparatus of the present invention notifies a user that one of a plurality of events has occurred, and includes a first reception unit, a second reception unit, a detection unit, and a light emitting unit. The first reception unit receives from the user, for each time slot that composes a light emission pattern, designation of a light emission color or non-emission, as a light emission attribute of the time slot. The second reception unit receives a designation of an event to be corresponded with the light emission pattern. The detection unit detects that one of the plurality of events has occurred. The light emitting unit, when the detection unit detects that the event has occurred, emits light based on the light emission pattern designated in correspondence with the event.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: December 19, 2006
    Assignees: Sanyo Electric Co., Ltd., Sanyo Telecommunications Co., ltd.
    Inventors: Yoji Hamada, Hiroko Nakamura
  • Patent number: 7148138
    Abstract: A method of forming a contact hole on a substrate by using a projection aligner comprising a lighting system including a light source, an aperture, and a condenser lens, a photo mask on which light from the lighting system is incident, and a projection lens for projecting the light from the photo mask onto the substrate, comprises forming a first photosensitive resist film on the substrate; exposing the first photosensitive resist film by using a photo mask in which mask patterns are cyclically arranged in a first direction and a second direction which is orthogonal to the first direction and a first aperture having light transmission parts arranged symmetrically with respect to a center point in the first direction; developing the exposed first photosensitive resist film to form first lines and linear spaces; forming a second photosensitive resist film on the substrate; exposing the second photosensitive resist film by using the photo mask and a second aperture having light transmission parts arranged symmet
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: December 12, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoji Mimotogi, Hiroko Nakamura, Kazuya Fukuhara, Satoshi Tanaka, Soichi Inoue
  • Patent number: 7026099
    Abstract: A pattern forming method is disclosed which comprises providing a to-be-processed film on a substrate, providing a resist film on the to-be-processed film, patterning the resist film, providing a film of a radiosensitive compound on the to-be-processed film such that the patterned resist film is covered with the film of the radiosensitive compound, subjecting the film of the radiosensitive compound to irradiation and a development process, thus exposing an upper surface of the resist film and patterning the film of the radiosensitive compound, and removing the resist film and processing the to-be-processed film, using the patterned film of the radiosensitive compound as a mask.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: April 11, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirokazu Kato, Yasunobu Onishi, Eishi Shiobara, Daisuke Kawamura, Hiroko Nakamura
  • Patent number: 7009440
    Abstract: The objective of this invention is to provide a pulse signal generator with a simple constitution that can reduce the number of signals required for setting the pulse width, as well as a display device using said pulse signal generator. Pulse assignment signal DP0 input to the initial stage of pulse signal generating units PG(i,0)–PG(i,39) connected in cascade is sequentially transferred towards the last stage of the cascade connection. After transfer of the pulse assignment signal to the pulse signal generating unit in each stage, the count value of said pulse signal generating unit is initialized. Then, the pulses of pulse strings PS0–PS39 in the various pulse signal generating units are counted. The count value of the pulse string is compared to the pulse assignment signal in the comparison unit of each pulse signal generating unit, and, in accordance with the comparison result, the level of the drive pulse signal of the LED is inverted.
    Type: Grant
    Filed: June 7, 2004
    Date of Patent: March 7, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Masashi Nogawa, Tetsuo Tateishi, Hiroko Nakamura
  • Publication number: 20050196684
    Abstract: A mask pattern data producing method is disclosed, which comprises preparing design pattern data in which contact holes are arranged on part of the grid points in matrix, preparing first mask pattern data in which first opening patterns are arranged on all of the grid points, and designing second mask pattern data in which second opening patterns and third opening patterns are arranged, the second opening patterns being arranged on the grid points at which the contact holes are arranged in the design pattern data to include the first opening patterns, the third opening patterns being arranged on a pair of grid points, which is a pair of diagonal grid points only on which the contact holes are arranged in a unit grid formed by four grid points, to include the first opening patterns arranged on the pair of grid points, in place of the second opening patterns.
    Type: Application
    Filed: February 22, 2005
    Publication date: September 8, 2005
    Inventors: Hiroko Nakamura, Toshiya Kotani, Satoshi Tanaka, Shoji Mimotogi
  • Publication number: 20050153540
    Abstract: A method of forming a contact hole on a substrate by using a projection aligner comprising a lighting system including a light source, an aperture, and a condenser lens, a photo mask on which light from the lighting system is incident, and a projection lens for projecting the light from the photo mask onto the substrate, comprises forming a first photosensitive resist film on the substrate; exposing the first photosensitive resist film by using a photo mask in which mask patterns are cyclically arranged in a first direction and a second direction which is orthogonal to the first direction and a first aperture having light transmission parts arranged symmetrically with respect to a center point in the first direction; developing the exposed first photosensitive resist film to form first lines and linear spaces; forming a second photosensitive resist film on the substrate; exposing the second photosensitive resist film by using the photo mask and a second aperture having light transmission parts arranged symmet
    Type: Application
    Filed: October 22, 2004
    Publication date: July 14, 2005
    Inventors: Shoji Mimotogi, Hiroko Nakamura, Kazuya Fukuhara, Satoshi Tanaka, Soichi Inoue
  • Publication number: 20050017778
    Abstract: The objective of this invention is to provide a pulse signal generator with a simple constitution that can reduce the number of signals required for setting the pulse width, as well as a display device using said pulse signal generator. Pulse assignment signal DP0 input to the initial stage of pulse signal generating units PG(i,0)-PG(i,39) connected in cascade is sequentially transferred towards the last stage of the cascade connection. After transfer of the pulse assignment signal to the pulse signal generating unit in each stage, the count value of said pulse signal generating unit is initialized. Then, the pulses of pulse strings PS0-PS39 in the various pulse signal generating units are counted. The count value of the pulse string is compared to the pulse assignment signal in the comparison unit of each pulse signal generating unit, and, in accordance with the comparison result, the level of the drive pulse signal of the LED is inverted.
    Type: Application
    Filed: June 7, 2004
    Publication date: January 27, 2005
    Inventors: Masashi Nogawa, Tetsuo Tateishi, Hiroko Nakamura
  • Publication number: 20040236548
    Abstract: A computer implemented method for development profile simulation in accordance with an embodiment of the present invention includes calculating optical intensities in a photosensitive resist, calculating a spatial average value of the optical intensities, reading a measured changing ratio of a dissolution rate of the photosensitive resist relating to an alkaline concentration changed by at least one of exposure dose on the photosensitive resist, a position in the thickness direction of the photosensitive resist and an alkaline concentration of developer for the photosensitive resist, obtaining a calculated dissolution rate by using the spatial average value and the measured changing ratio, and predicting a pattern shape of the photosensitive resist from the calculated dissolution rate.
    Type: Application
    Filed: January 21, 2004
    Publication date: November 25, 2004
    Inventors: Hiroko Nakamura, Shoji Mimotogi, Yasunobu Onishi
  • Publication number: 20030215749
    Abstract: A pattern forming method is disclosed which comprises providing a to-be-processed film on a substrate, providing a resist film on the to-be-processed film, patterning the resist film, providing a film of a radiosensitive compound on the to-be-processed film such that the patterned resist film is covered with the film of the radiosensitive compound, subjecting the film of the radiosensitive compound to irradiation and a development process, thus exposing an upper surface of the resist film and patterning the film of the radiosensitive compound, and removing the resist film and processing the to-be-processed film, using the patterned film of the radiosensitive compound as a mask.
    Type: Application
    Filed: April 22, 2003
    Publication date: November 20, 2003
    Inventors: Hirokazu Kato, Yasunobu Onishi, Eishi Shiobara, Daisuke Kawamura, Hiroko Nakamura
  • Patent number: 6632476
    Abstract: After a thin liquid agent film is formed by supplying a liquid agent onto a plate-like developer holder, this liquid agent film and the surface of a substrate are opposed. The liquid agent film and the substrate are brought into contact with each other at a point by declining the substrate and moving it close to the liquid agent film, or by curving the substrate toward the liquid agent film. Then, the substrate is made parallel to the liquid agent film, and the liquid agent is supplied such that the contact area of the liquid agent film spreads over the entire surface by the interfacial tension between the liquid agent film and the substrate. Since a thin liquid agent film can be uniformly formed below the substrate, processing can be performed with a small consumption amount. Additionally, the liquid agent can be supplied to the substrate without holding air.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: October 14, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroko Nakamura, Hisashi Kaneko, Tetsuo Matsuda