Patents by Inventor Hiromi Notani
Hiromi Notani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10317981Abstract: A data processing device includes a load circuit including a central processing unit and operated by supplied electric power, a step-down power supply circuit stepping down an external power supply voltage and including an output node coupled to the load circuit, the step-down power supply circuit including a first step-down unit stepping down the external power supply voltage, and a bias current control circuit controlling a magnitude of bias current flowing through an auxiliary path from the output node to a ground, the auxiliary path is separate from a path to the load circuit, and a control circuit increasing the magnitude of the bias current, prior to a change of an operation state of the load circuit by which a relatively large change occurs to an amount of current consumed by the load circuit.Type: GrantFiled: December 6, 2016Date of Patent: June 11, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Soichi Kobayashi, Akira Oizumi, Yoshihiko Yasu, Hiromi Notani
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Patent number: 10268250Abstract: A semiconductor device having an active mode and a standby mode as operation modes, includes a first power supply line supplied with a first internal power supply voltage from a first external power supply and an internal power supply circuit generating a second internal power supply voltage based on an external power supply voltage from a second external power supply circuit. A second power supply line supplied with said second internal power supply voltage from said internal power supply circuit.Type: GrantFiled: July 13, 2017Date of Patent: April 23, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiromi Notani, Takayuki Fukuoka, Takashi Yamaki
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Publication number: 20170308138Abstract: A semiconductor device having an active mode and a standby mode as operation modes, includes a first power supply line supplied with a first internal power supply voltage from a first external power supply and an internal power supply circuit generating a second internal power supply voltage based on an external power supply voltage from a second external power supply circuit. A second power supply line supplied with said second internal power supply voltage from said internal power supply circuit.Type: ApplicationFiled: July 13, 2017Publication date: October 26, 2017Inventors: Hiromi Notani, Takayuki Fukuoka, Takashi Yamaki
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Patent number: 9727106Abstract: In an active mode, a VDD line receives an internal power supply voltage from an external regulator. A VDD_RAM line receives an internal power supply voltage from an internal regulator. A PMOS switch includes a first PMOS transistor having a source and an N-type well connected to the VDD line, and a second PMOS transistor having a source and an N-type well connected to the VDD_RAM line and a drain connected to a drain of the first PMOS transistor. The first PMOS transistor is controlled based on a control command from a system control circuit and a voltage of the VDD_RAM line. The second PMOS transistor is controlled based on the control command and a voltage of the VDD line.Type: GrantFiled: December 19, 2013Date of Patent: August 8, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiromi Notani, Takayuki Fukuoka, Takashi Yamaki
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Publication number: 20170083080Abstract: A data processing device includes a load circuit including a central processing unit and operated by supplied electric power, a step-down power supply circuit stepping down an external power supply voltage and including an output node coupled to the load circuit, the step-down power supply circuit including a first step-down unit stepping down the external power supply voltage, and a bias current control circuit controlling a magnitude of bias current flowing through an auxiliary path from the output node to a ground, the auxiliary path is separate from a path to the load circuit, and a control circuit increasing the magnitude of the bias current, prior to a change of an operation state of the load circuit by which a relatively large change occurs to an amount of current consumed by the load circuit.Type: ApplicationFiled: December 6, 2016Publication date: March 23, 2017Inventors: Soichi Kobayashi, Akira Oizumi, Yoshihiko Yasu, Hiromi Notani
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Patent number: 9529402Abstract: A step down unit steps down an external power supply voltage Vcc. A bias current control circuit controls the magnitude of bias current flowing through an auxiliary path connecting an output node and the ground. A system controller increases the magnitude of the bias current, prior to a change of the operation state of a load circuit by which a relatively large change occurs to the amount of current consumed by the load circuit including a central processing unit.Type: GrantFiled: September 2, 2010Date of Patent: December 27, 2016Assignee: Renesas Electronics CorporationInventors: Soichi Kobayashi, Akira Oizumi, Yoshihiko Yasu, Hiromi Notani
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Patent number: 9274537Abstract: There is provided a regulator circuit capable of increasing the capacity of the output transistor for supplying current, stably generating an internal power supply voltage and adapting to the reduction of a power supply voltage. The regulator circuit includes an output transistor which is supplied with an external power supply voltage and supplies dropped voltage to an internal circuit, a differential amplifier for outputting a gate potential applied to the gate of the output transistor, a reference voltage generating circuit for supplying a reference voltage to the differential amplifier, and a cut-off transistor for turning off the output transistor to stop supplying power to the internal circuit. The output transistor is comprised of a depression NMOS transistor whose threshold voltage is a negative voltage. The regulator circuit further includes substrate potential control means for controlling the substrate potential of the depression NMOS transistor.Type: GrantFiled: December 8, 2014Date of Patent: March 1, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Hiromi Notani
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Publication number: 20150091542Abstract: There is provided a regulator circuit capable of increasing the capacity of the output transistor for supplying current, stably generating an internal power supply voltage and adapting to the reduction of a power supply voltage. The regulator circuit includes an output transistor which is supplied with an external power supply voltage and supplies dropped voltage to an internal circuit, a differential amplifier for outputting a gate potential applied to the gate of the output transistor, a reference voltage generating circuit for supplying a reference voltage to the differential amplifier, and a cut-off transistor for turning off the output transistor to stop supplying power to the internal circuit. The output transistor is comprised of a depression NMOS transistor whose threshold voltage is a negative voltage. The regulator circuit further includes substrate potential control means for controlling the substrate potential of the depression NMOS transistor.Type: ApplicationFiled: December 8, 2014Publication date: April 2, 2015Inventor: Hiromi NOTANI
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Patent number: 8917071Abstract: There is provided a regulator circuit capable of increasing the capacity of the output transistor for supplying current, stably generating an internal power supply voltage and adapting to the reduction of a power supply voltage. The regulator circuit includes an output transistor which is supplied with an external power supply voltage and supplies dropped voltage to an internal circuit, a differential amplifier for outputting a gate potential applied to the gate of the output transistor, a reference voltage generating circuit for supplying a reference voltage to the differential amplifier, and a cut-off transistor for turning off the output transistor to stop supplying power to the internal circuit. The output transistor is comprised of a depression NMOS transistor whose threshold voltage is a negative voltage. The regulator circuit further includes substrate potential control means for controlling the substrate potential of the depression NMOS transistor.Type: GrantFiled: April 11, 2013Date of Patent: December 23, 2014Assignee: Renesas Electronics CorporationInventor: Hiromi Notani
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Publication number: 20140189381Abstract: In an active mode, a VDD line receives an internal power supply voltage from an external regulator. A VDD_RAM line receives an internal power supply voltage from an internal regulator. A PMOS switch includes a first PMOS transistor having a source and an N-type well connected to the VDD line, and a second PMOS transistor having a source and an N-type well connected to the VDD_RAM line and a drain connected to a drain of the first PMOS transistor. The first PMOS transistor is controlled based on a control command from a system control circuit and a voltage of the VDD_RAM line. The second PMOS transistor is controlled based on the control command and a voltage of the VDD line.Type: ApplicationFiled: December 19, 2013Publication date: July 3, 2014Applicant: Renesas Electronics CorporationInventors: Hiromi Notani, Takayuki Fukuoka, Takashi Yamaki
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Publication number: 20130234689Abstract: There is provided a regulator circuit capable of increasing the capacity of the output transistor for supplying current, stably generating an internal power supply voltage and adapting to the reduction of a power supply voltage. The regulator circuit includes an output transistor which is supplied with an external power supply voltage and supplies dropped voltage to an internal circuit, a differential amplifier for outputting a gate potential applied to the gate of the output transistor, a reference voltage generating circuit for supplying a reference voltage to the differential amplifier, and a cut-off transistor for turning off the output transistor to stop supplying power to the internal circuit. The output transistor is comprised of a depression NMOS transistor whose threshold voltage is a negative voltage. The regulator circuit further includes substrate potential control means for controlling the substrate potential of the depression NMOS transistor.Type: ApplicationFiled: April 11, 2013Publication date: September 12, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Hiromi NOTANI
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Publication number: 20130159746Abstract: A step down unit steps down an external power supply voltage Vcc. A bias current control circuit controls the magnitude of bias current flowing through an auxiliary path connecting an output node and the ground. A system controller increases the magnitude of the bias current, prior to a change of the operation state of a load circuit by which a relatively large change occurs to the amount of current consumed by the load circuit including a central processing unit.Type: ApplicationFiled: September 2, 2010Publication date: June 20, 2013Applicant: Renesas Electronics CorporationInventors: Soichi Kobayashi, Akira Oizumi, Yoshihiko Yasu, Hiromi Notani
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Patent number: 8432144Abstract: There is provided a regulator circuit capable of increasing the capacity of the output transistor for supplying current, stably generating an internal power supply voltage and adapting to the reduction of a power supply voltage. The regulator circuit includes an output transistor which is supplied with an external power supply voltage and supplies dropped voltage to an internal circuit, a differential amplifier for outputting a gate potential applied to the gate of the output transistor, a reference voltage generating circuit for supplying a reference voltage to the differential amplifier, and a cut-off transistor for turning off the output transistor to stop supplying power to the internal circuit. The output transistor is comprised of a depression NMOS transistor whose threshold voltage is a negative voltage. The regulator circuit further includes substrate potential control means for controlling the substrate potential of the depression NMOS transistor.Type: GrantFiled: June 21, 2011Date of Patent: April 30, 2013Assignee: Renesas Electronics CorporationInventor: Hiromi Notani
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Patent number: 8378739Abstract: The present invention provides a semiconductor chip which is insusceptible to noise and whose consumption current is small. In a semiconductor chip, an internal power supply voltage for an internal circuit block is generated by a regulator having small current drive capability and a regulator having large current drive capability. A voltage buffer is provided between a reference voltage generating circuit and the regulator having large current drive capability. In a low-speed operation mode, the voltage buffer and the regulator having large current drive capability are made inactive. Therefore, noise in reference voltage is suppressed, and consumption current can be reduced.Type: GrantFiled: July 15, 2011Date of Patent: February 19, 2013Assignee: Renesas Electronics CorporationInventors: Hiromi Notani, Issei Kashima
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Publication number: 20120049899Abstract: The present invention provides a semiconductor chip which is insusceptible to noise and whose consumption current is small. In a semiconductor chip, an internal power supply voltage for an internal circuit block is generated by a regulator having small current drive capability and a regulator having large current drive capability. A voltage buffer is provided between a reference voltage generating circuit and the regulator having large current drive capability. In a low-speed operation mode, the voltage buffer and the regulator having large current drive capability are made inactive. Therefore, noise in reference voltage is suppressed, and consumption current can be reduced.Type: ApplicationFiled: July 15, 2011Publication date: March 1, 2012Inventors: Hiromi Notani, Issei Kashima
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Publication number: 20110309819Abstract: There is provided a regulator circuit capable of increasing the capacity of the output transistor for supplying current, stably generating an internal power supply voltage and adapting to the reduction of a power supply voltage. The regulator circuit includes an output transistor which is supplied with an external power supply voltage and supplies dropped voltage to an internal circuit, a differential amplifier for outputting a gate potential applied to the gate of the output transistor, a reference voltage generating circuit for supplying a reference voltage to the differential amplifier, and a cut-off transistor for turning off the output transistor to stop supplying power to the internal circuit. The output transistor is comprised of a depression NMOS transistor whose threshold voltage is a negative voltage. The regulator circuit further includes substrate potential control means for controlling the substrate potential of the depression NMOS transistor.Type: ApplicationFiled: June 21, 2011Publication date: December 22, 2011Inventor: Hiromi NOTANI
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Patent number: 7345936Abstract: A data storage circuit having a plurality of memory cells (S1), a plurality of bit lines (BL, /BL) and a precharge circuit further comprises a discharge circuit. In an operating mode of the data storage circuit, the bit lines (BL, /BL) are precharged by the precharge circuit under the control on the basis of a chip enable signal (CE) before write or read of data into/from the memory cells (S1) and in a standby state, the bit lines (BL, /BL) are discharged by the discharge circuit. Further, also in a sleep mode, the bit lines (BL, /BL) are discharged by the discharge circuit. With this circuit configuration and operation, it is possible to provide the data storage circuit which allows reduction in standby power consumption by suppressing standby currents in the standby state.Type: GrantFiled: December 19, 2003Date of Patent: March 18, 2008Assignee: Renesas Technology Corp.Inventor: Hiromi Notani
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Patent number: 6998668Abstract: A semiconductor integrated circuit device is provided, in which a node from which an output signal of a level shifter is sent can be initialized such that the potential thereof be set at a desired logic level at the time of power supply. The semiconductor integrated circuit device includes a level shifter 6 and two capacitors N10 and C0. The level shifter 6 receives an input signal and converts the received signal to a signal having a voltage amplitude greater than that of the received signal, then to provide the signal to a node D3. The capacitor N10 is connected to the node D3, and the capacitor C0 is connected in series with the capacitor N10. The capacitor N10 is formed of a MOS transistor having a gate connected to the node D3 and a source and a drain both connected to the capacitor C0.Type: GrantFiled: September 19, 2002Date of Patent: February 14, 2006Assignee: Renesas Technology Corp.Inventors: Yasunobu Nakase, Hiromi Notani
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Publication number: 20040243758Abstract: A data storage circuit having a plurality of memory cells (S1), a plurality of bit lines (BL, /BL) and a precharge circuit further comprises a discharge circuit. In an operating mode of the data storage circuit, the bit lines (BL, /BL) are precharged by the precharge circuit under the control on the basis of a chip enable signal (CE) before write or read of data into/from the memory cells (S1) and in a standby state, the bit lines (BL, /BL) are discharged by the discharge circuit. Further, also in a sleep mode, the bit lines (BL, /BL) are discharged by the discharge circuit. With this circuit configuration and operation, it is possible to provide the data storage circuit which allows reduction in standby power consumption by suppressing standby currents in the standby state.Type: ApplicationFiled: December 19, 2003Publication date: December 2, 2004Applicant: Renesas Technology Corp.Inventor: Hiromi Notani
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Patent number: 6795333Abstract: A memory cell in the SRAM has three storing/holding states, i.e., a state where two storage nodes store 0, 1, a state where the two storage nodes store 1, 0, and a state where the two storage nodes store 1, 1. Therefore, the number of memory cells can be reduced by one half compared to the conventional case in which two memory cells were required to store three types of data signals.Type: GrantFiled: January 7, 2003Date of Patent: September 21, 2004Assignee: Renesas Technology Corp.Inventor: Hiromi Notani