Abstract: Backgate biases of MOS transistors for generating a bias voltage in a bias voltage generation circuit generating the bias voltages are set shallow and backgate biases of MOS transistors of delay circuits of a ring oscillator constituting a clock generation circuit are set shallow. Thereby, a voltage range and a frequency range of a voltage controlled generation circuit to implement a phase synchronizing loop are both extended.

Abstract: A bias potential generation circuit in a level conversion circuit sets a bias potential applied to the backgate of an N-channel MOS transistor for pull-down at a positive potential when an input signal is set at the “L” level and the first and second signals are set at the “H” and “L” levels respectively, to lower the threshold voltage of the N-channel MOS transistor. Therefore, even if an amplitude voltage of the input signal is lowered, the operating speed can be increased.

Abstract: A memory cell in the SRAM has three storing/holding states, i.e., a state where two storage nodes store 0, 1; a state where the two storage nodes store 1, 0, and a state where the two storage nodes store 1, 1. Therefore, the number of memory cells can be reduced to a half compared to the conventional case where two memory cells were required to store three types of data signals.

Abstract: A bias potential generation circuit in a level conversion circuit sets a bias potential applied to the backgate of an N-channel MOS transistor for pull-down at a positive potential when an input signal is set at the “L” level and the first and second signals are set at the “H” and “L” levels respectively, to lower the threshold voltage of the N-channel MOS transistor. Therefore, even if an amplitude voltage of the input signal is lowered, the operating speed can be increased.

Abstract: A semiconductor integrated circuit device is provided, in which a node from which an output signal of a level shifter is sent can be initialized such that the potential thereof be set at a desired logic level at the time of power supply.

Abstract: When an up signal UP is inputted, a switch is turned on and thereby a capacitor is charged to raise a control voltage VC. Further, when a down signal DWN is inputted, a switch is turned on and a capacitor discharges to hold the down signal DWN in the capacitor. Then, when a switch is turned on by a transmission signal EXE, an electric charge is injected into the capacitor to lower the control voltage VC. Further, when a switch is turned on by a reset signal RST, the capacitor is charged by an amplifier to cancel the down signal DWN. As a result, a low jitter reproduction clock can be generated regardless of an operating frequency.

Abstract: A semiconductor integrated circuit includes: a first MOS transistor having one source/drain electrode for receiving a power supply voltage and the other source/drain electrode connected to a virtual power supply line; a second MOS transistor having one source/drain electrode connected to the virtual power supply line and the other source/drain electrode connected to a backgate power supply line; and a third MOS transistor having one source/drain electrode connected to the virtual power supply line and the backgate electrode connected to the backgate power supply line. When the first and second transistors are turned on, a voltage of the backgate electrode is forwardly biased to the one source/drain electrode in the third MOS transistor, thereby improving the operation speed of an internal circuit including the third MOS transistors in an active period.

Abstract: On a sleep state, a voltage dropping circuit 2 supplies a power supply line VA1 with a voltage obtained by dropping a voltage of a power supply line VA2, instead of a voltage in accordance with ON state of a switch QA1. A power supply line GND has a voltage equal to the ground voltage. A charge pump circuit 10 outputs the ground voltage on an active state. The charge pump circuit 10 outputs a voltage which is lower than the ground voltage, on the sleep state. A source electrode and a substrate electrode are connected to the power supply lines VA1 and VA2 in each of PMOS transistors Q3 and Q4 of an internal circuit 1 (latch circuit), respectively. A source electrode is connected to the power supply line GND in each of nMOS transistors Q5 and Q6 of the internal circuit 1. A substrate electrode is supplied with the voltage which is outputted from the charge pump circuit, in each of the nMOS transistors Q5 and Q6 of the internal circuit 1.

Abstract: On a sleep state, a voltage dropping circuit 2 supplies a power supply line VA1 with a voltage obtained by dropping a voltage of a power supply line VA2, instead of a voltage in accordance with ON state of a switch QA1. A power supply line GND has a voltage equal to the ground voltage. A charge pump circuit 10 outputs the ground voltage on an active state. The charge pump circuit 10 outputs a voltage which is lower than the ground voltage, on the sleep state. A source electrode and a substrate electrode are connected to the power supply lines VA1 and VA2 in each of pMOS transistors Q3 and Q4 of an internal circuit 1 (latch circuit), respectively. A source electrode is connected to the power supply line GND in each of nMOS transistors Q5 and Q6 of the internal circuit 1. A substrate electrode is supplied with the voltage which is outputted from the charge pump circuit, in each of the NMOS transistors Q5 and Q6 of the internal circuit 1.

Abstract: Backgate biases of MOS transistors for generating a bias voltage in a bias voltage generation circuit generating the bias voltages are set shallow and backgate biases of MOS transistors of delay circuits of a ring oscillator constituting a clock generation circuit are set shallow. Thereby, a voltage range and a frequency range of a voltage controlled generation circuit to implement a phase synchronizing loop are both extended.

Abstract: A digital data transmission system for transmitting digital data, a frame pulse signal, and a clock using a required minimum number of signal lines and with a simple circuit structure is provided. A signal separation circuit (46) that receives a multiple clock (CKFP) which is a frame pulse signal (FP) multiplexed with a clock (CK) includes a clock recovery circuit (47) for reproducing a recovered clock (RCK) by synchronization with the multiple clock (CKFP) using a synchronization loop, and a frame pulse signal separation circuit (48) for separating a recovered frame pulse signal (RFP) from the multiple clock (CKFP) on the basis of the recovered clock (RCK).

Abstract: When an up signal UP is inputted, a switch is turned on and thereby a capacitor is charged to raise a control voltage VC. Further, when a down signal DWN is inputted, a switch is turned on and a capacitor discharges to hold the down signal DWN in the capacitor. Then, when a switch is turned on by a transmission signal EXE, an electric charge is injected into the capacitor to lower the control voltage VC. Further, when a switch is turned on by a reset signal RST, the capacitor is charged by an amplifier to cancel the down signal DWN. As a result, a low jitter reproduction clock can be generated regardless of an operating frequency.

Abstract: A semiconductor integrated circuit comprises: a first MOS transistor having one source/drain electrode for receiving a power supply voltage and the other source/drain electrode connected to a virtual power supply line; a second MOS transistor having one source/drain electrode connected to the virtual power supply line and the other source/drain electrode connected to a backgate power supply line; and a third MOS transistor having one source/drain electrode connected to the virtual power supply line and the backgate electrode connected to the backgate power supply line. When the first and second transistors are turned on, a voltage of the backgate electrode is forwardly biased to the one source/drain electrode in the third MOS transistor, thereby improving the operation speed of an internal circuit including the third MOS transistors in an active period.

Abstract: Provided is a DLL circuit that can execute a precise delay synchronization operation without increasing the variable delay time range of a delay line. The DLL circuit comprises a phase comparator (3), a charge pump (6), an LPF (8) and a delay line (9), and operates to match phases of an input signal (CLKIN) and a feedback signal (FBCLK). The phase comparator (3) always outputs a phase comparison result that causes a delay time of the delay line (9) to increase, at the time of initial operation after a reset operation. The LPF (8) outputs a delay adjusting signal (S8) indicating that a delay time due to the delay line (9) becomes the minimum, in executing a reset.

Abstract: The operating speed of an apparatus which operates with a clock is increased by obtaining a clock having a constant duty ratio. The maximum variable delay quantity of a first variable delay circuit 11 is set more than one cycle and less than two cycles of an input clock IN. The delay quantities of the first and second variable delay circuits 11, 12 are decreased with a control signal Vin. In addition, the ratio of the delay quantity of the second variable delay circuit 12 to that of the first variable delay circuit 11 is set to a constant value which is less than 1. A control portion 13 increases and decreases the control signal Vin in such a manner that the phases of an input clock IN and an output clock OUT-A of the first variable delay circuit are coincident with each other. An output clock OUT of the device is set by the output clock OUT-A of the first variable delay circuit, and is reset by an output clock OUT-B of the second variable delay circuit.

Abstract: A voltage applying means applies a voltage which determines the logical value of a node to the node, with the signal at the node fixed. Then, an applied voltage removing means removes the voltage applied by the voltage applying means. First and second detecting means detects the logical value of the node before and after the voltage application and removal of the applied voltage. A judging means compares the results of detection of the first and second detecting means to judge whether or not the node is at a high impedance.

Abstract: A current type inverter circuit used in a Current Type Ring Oscillator and a Voltage-Controlled oscillator operates at a high speed with a low power consumption. A reference power source 1 has one end connected to a power source VDD and the other source receiving a reference current Iref. A drain and a gate of an NMOS transistor Q1 of a current mirror circuit CM1, as an input part, receive an input current Iin. A drain of an NMOS transistor Q2 is connected to an node N1 of the other end side of the reference power source 1 as an output part. As an input part, a drain and a gate of an NMOS transistor Q3 of a current mirror circuit CM2 are connected to the node N1 while a drain of an NMOS transistor Q4 functions as an output part for outputting an output current Iout. The transistors are set so that all of the conditions TS1.gtoreq.1, TS2.gtoreq.1 and TS1.multidot.

Abstract: A current type inverter circuit or the like is obtained which operates at a high speed with a low power consumption. A reference power source 1 has one end connected to a power source VDD and the other source receiving a reference current Iref. A drain and a gate of an NMOS transistor Q1 of a current mirror circuit CM1, as an input part, receive an input current Iin. A drain of an NMOS transistor Q2 is connected to an node N1 of the other end side of the reference power source 1 as an output part. As an input part, a drain and a gate of an NMOS transistor Q3 of a current mirror circuit CM2 are connected to the node N1 while a drain of an NMOS transistor Q4 functions as an output part for outputting an output current Iout. The transistors are set so that all of the conditions TS1.gtoreq.1, TS2.gtoreq.1 and TS1.multidot.

Abstract: A plurality of shift memories shifting data are connected in series, destination indicating bits indicative of data destination are stored in destination indicating bit memories corresponding to the shift memories respectively, and a searching circuit is provided adjacent to each of the destination indicating bit memories, which searching circuit searches data by searching the destination indicating bits.

Abstract: A VCO circuit 4 of a PLL circuit 1 includes M delay time variable inverters 5.1 to 5.M which are connected in a ring shape. Load driving capability of delay time variable inverters 5.1 to 5.M is increased gradually toward output node OUT which is connected directly to load capacity CL. Accordingly, a high load driving capability is obtained without provision of a separate buffer.