Abstract: It is an object of the present invention to provide a phase comparator which can compare phase at high speed with simple structure. The phase is compared by a precharge type NAND gate including transistors (Q35-Q37). The result of comparison in the NAND gate is then outputted only in a period in which the input clock CLKref is at "1" by the NAND gate (NA 15), and thus the phase lag of the internal clock CLKint with respect to the input clock CLKref is detected. Phase lead of the internal clock CLKint with respect to the input clock CLKref is compared with interchanged relation of clocks inputted to a phase detecting portion (PD 2). Phase comparison can be made at high speed with a simple circuit including the precharge type NAND gate and the NAND gate (NA 15).

Abstract: Current I.sub.P through a transistor 2 linearly decreases according to control voltage V.sub.I in the range from 0 to V.sub.DD -V.sub.TP. Current I.sub.N through a transistor 3 linearly increases according to control voltage V.sub.I in the range from V.sub.TN to V.sub.DD. In a subtraction/inversion circuit 5, constant current I.sub.CONST is introduced, I.sub.P is subtracted therefrom, and .DELTA.I having an inclination in the same direction as I.sub.N is produced. Bias current I.sub.B serially changing in the range of V.sub.I from 0 to V.sub.DD passes through a transistor 7. Accordingly, even if control voltage V.sub.I is smaller than the threshold voltage V.sub.TN of an input transistor, current I.sub.B or voltages V.sub.PP and V.sub.BN which linearly change according to control voltage V.sub.I are output.

Abstract: Each of a plurality of buffer memories provided corresponding to a plurality of OUT line fetches a cell through a corresponding address filter and provides the fetched cell to the corresponding OUT line, in normal operation. When any of the buffer memories become full, a spare buffer memory operates in place of the buffer memory, fetches the cell through a corresponding variable buffer memory, and provides the fetched cell to the corresponding OUT line. Such control is effected by a control circuit. Accordingly, in an ATM switch, increase of hardware related to the storage of information and lowering of efficiency in use can be suppressed as much as possible, and the ratio of disposal of the cells can be reduced.

Abstract: A data queuing apparatus processes data switching and queuing using a smaller capacity memory, while reducing data discard and loss possibility. Received limited-length data at the input line is written in shift memories, which can shift the data to the next stage regardless of the destination of the data. Destination indicating bits, which indicate the destination of the data, are associated with each of shift memories. A search circuit detects an asserted bit among the destination indicating bits corresponding to the output lines. The data is extracted by a selector. Then the selector transmits the data to the desired output line, and the data stored in the previous stage of the shift memory is shifted. The memory is used in common with a plurality of output lines, so that a lower possibility of data discard and loss can be attained in a smaller capacity memory.

Abstract: A crosspoint LSI adapted to an exchanger in ISDN, for transmission of asynchronous transfer mode (ATM) cells in communication is provided. The crosspoint switching LSI includes many unit switch cells arranged in rows and columns. When a unit switch cell is turned on, the unit switch cell responds to a differential data signal on an input data line to drive differentially an output data line pair. The unit switch cells operate differentially so that the data signals of the ATM cells are transmitted, which improves a signal transmission rate.

Abstract: Incoming lines (I0 to I7) are connected to a space switch (2) through input data latches (1). The space switch (2) is connected to a normal/test changeover switch (12), which is connected to a normal/test changeover switch (13) through serial-to-parallel converting circuits (3), common buffer memories (4) and parallel-to-serial converting circuits (5). Space switches (6) are connected to the normal/test changeover switch (13). Outgoing lines (O0 to O7) are connected to the space switches 6 through output data latches (8). Connection states in the switches (2, 6) are placed in transposed relation to each other by a transposed connection generating circuit (10) in a test operation, so that the switches (2, 6) are directly connected to each other through the switches (12, 13). Predetermined data applied to the incoming lines are intactly used as expected values for judgement of the normal or abnormal operation of the set of switches of matrix structure.

Abstract: A ratio latch included in each slave latch is formed of a tri-state inverter and a weak inverter. During a period when a parallel input signal is supplied to the ratio latch in each master latch in response to a trigger clock signal, the tri-state inverter attains a high impedance state in response to an inverted trigger clock signal.

Abstract: An output circuit 1 comprises a constant current source 11, a switch 12, and an output pad 14. The switch 12 is connected between the constant current source 11 and the output pad 14. A transmission path 3 is connected to the output pad 14. The transmission path 3 is coupled to a terminator voltage V.sub.TT by a resistor for pull up. Reflection of a signal or generation of noise can be suppressed by bringing the resistance value of the resistor 4 close to a characteristic impedance of the transmission path 3. A voltage amplitude on the transmission path 3 can be determined arbitrarily by adjusting current value of the constant current source 11 and resistance value of the resistor 4.