Patents by Inventor Hiromi Ogata
Hiromi Ogata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8310737Abstract: An image reading apparatus of the present invention includes a first light source, a first light guide, a second light source, a second light guide, light receiving elements and a lens unit. The first light source emits first light. The first light guide directs the first light from the first light source toward an image-carrying object as first linear light extending in a primary scanning direction. The second light source emits second light of a wavelength different from that of the first light. The second light guide directs the second light from the second light source toward the image-carrying object as second linear light extending in the primary scanning direction. The light receiving elements are arranged in the primary scanning direction. The first and second linear lights are reflected by the image-carrying object, and the reflected lights are guided by the lens unit toward the light receiving elements.Type: GrantFiled: August 20, 2009Date of Patent: November 13, 2012Assignee: Rohm Co., Ltd.Inventors: Yasuhiro Nagao, Hideki Sawada, Hiromi Ogata, Yasuyuki Aritaki, Hiroyuki Tajiri, Hiroki Kawai
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Patent number: 8299818Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.Type: GrantFiled: April 12, 2011Date of Patent: October 30, 2012Assignee: Sony CorporationInventor: Hiromi Ogata
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Publication number: 20120256683Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.Type: ApplicationFiled: February 13, 2012Publication date: October 11, 2012Applicant: Sony CorporationInventor: Hiromi Ogata
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Patent number: 8143914Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.Type: GrantFiled: January 6, 2011Date of Patent: March 27, 2012Assignee: Sony CorporationInventor: Hiromi Ogata
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Publication number: 20110193618Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.Type: ApplicationFiled: April 12, 2011Publication date: August 11, 2011Applicant: Sony CorporationInventor: Hiromi Ogata
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Patent number: 7956677Abstract: A semiconductor integrated circuit includes: a first voltage line on which a specific one of a power-supply voltage and a reference voltage appears; a second voltage line; a plurality of circuit cells each receiving power generated as a difference between a voltage appearing on the second voltage line and the other one of the power-supply voltage and the reference voltage; a plurality of switch transistors connected in parallel between the first and second voltage lines to serve as switch transistors including switch transistors each having different conducting-state resistances; and a switch conduction control section for controlling a transition of each of the switch transistors from a non-conducting state to a conducting state by turning on the switch transistors at separate points of time.Type: GrantFiled: January 13, 2009Date of Patent: June 7, 2011Assignee: Sony CorporationInventors: Masahiro Igarashi, Tetsuo Motomura, Ryuji Kaneko, Makoto Fujiwara, Yoshinori Tanaka, Hiromi Ogata
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Patent number: 7944243Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.Type: GrantFiled: January 21, 2010Date of Patent: May 17, 2011Assignee: Sony CorporationInventor: Hiromi Ogata
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Patent number: 7940080Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.Type: GrantFiled: August 22, 2008Date of Patent: May 10, 2011Assignee: Sony CorporationInventor: Hiromi Ogata
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Publication number: 20110102076Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.Type: ApplicationFiled: January 6, 2011Publication date: May 5, 2011Applicant: Sony CorporationInventor: Hiromi Ogata
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Patent number: 7786793Abstract: Disclosed herein is a semiconductor integrated circuit including a stoppable circuit unit configured to be alternately switched between a stopped state and an operating state; a first voltage line configured to apply a first voltage to the stoppable circuit unit when the stoppable circuit unit is in the operating state; a second voltage line configured to apply the first voltage to the stoppable circuit unit when the stoppable circuit unit is in a transient state of switching from the stopped state to the operating state; and a third voltage line configured to apply a second voltage to the stoppable circuit unit.Type: GrantFiled: June 2, 2008Date of Patent: August 31, 2010Assignee: Sony CorporationInventor: Hiromi Ogata
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Patent number: 7750681Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.Type: GrantFiled: October 2, 2008Date of Patent: July 6, 2010Assignee: Sony CorporationInventor: Hiromi Ogata
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Publication number: 20100123481Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.Type: ApplicationFiled: January 21, 2010Publication date: May 20, 2010Applicant: Sony CorporationInventor: Hiromi Ogata
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Patent number: 7696788Abstract: A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells.Type: GrantFiled: October 30, 2008Date of Patent: April 13, 2010Inventor: Hiromi Ogata
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Publication number: 20100046045Abstract: An image reading apparatus of the present invention includes a first light source, a first light guide, a second light source, a second light guide, light receiving elements and a lens unit. The first light source emits first light. The first light guide directs the first light from the first light source toward an image-carrying object as first linear light extending in a primary scanning direction. The second light source emits second light of a wavelength different from that of the first light. The second light guide directs the second light from the second light source toward the image-carrying object as second linear light extending in the primary scanning direction. The light receiving elements are arranged in the primary scanning direction. The first and second linear lights are reflected by the image-carrying object, and the reflected lights are guided by the lens unit toward the light receiving elements.Type: ApplicationFiled: August 20, 2009Publication date: February 25, 2010Applicant: ROHM CO., LTD.Inventors: Yasuhiro NAGAO, Hideki SAWADA, Hiromi OGATA, Yasuyuki ARITAKI, Hiroyuki TAJIRI, Hiroki KAWAI
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Publication number: 20090179688Abstract: A semiconductor integrated circuit includes: a first voltage line on which a specific one of a power-supply voltage and a reference voltage appears; a second voltage line; a plurality of circuit cells each receiving power generated as a difference between a voltage appearing on the second voltage line and the other one of the power-supply voltage and the reference voltage; a plurality of switch transistors connected in parallel between the first and second voltage lines to serve as switch transistors including switch transistors each having different conducting-state resistances; and a switch conduction control section for controlling a transition of each of the switch transistors from a non-conducting state to a conducting state by turning on the switch transistors at separate points of time.Type: ApplicationFiled: January 13, 2009Publication date: July 16, 2009Applicant: Sony CorporationInventors: Masahiro Igarashi, Tetsuo Motomura, Ryuji Kaneko, Makoto Fujiwara, Yoshinori Tanaka, Hiromi Ogata
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Publication number: 20090115394Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.Type: ApplicationFiled: October 2, 2008Publication date: May 7, 2009Applicant: Sony CorporationInventor: Hiromi Ogata
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Publication number: 20090079469Abstract: A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells.Type: ApplicationFiled: October 30, 2008Publication date: March 26, 2009Applicant: Sony CorporationInventor: Hiromi Ogata
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Publication number: 20090072888Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.Type: ApplicationFiled: August 22, 2008Publication date: March 19, 2009Applicant: Sony CorporationInventor: Hiromi Ogata
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Publication number: 20090009238Abstract: Disclosed herein is a semiconductor integrated circuit including a stoppable circuit unit configured to be alternately switched between a stopped state and an operating state; a first voltage line configured to apply a first voltage to the stoppable circuit unit when the stoppable circuit unit is in the operating state; a second voltage line configured to apply the first voltage to the stoppable circuit unit when the stoppable circuit unit is in a transient state of switching from the stopped state to the operating state; and a third voltage line configured to apply a second voltage to the stoppable circuit unit.Type: ApplicationFiled: June 2, 2008Publication date: January 8, 2009Applicant: Sony CorporationInventor: Hiromi Ogata
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Patent number: RE43912Abstract: A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells.Type: GrantFiled: December 29, 2011Date of Patent: January 8, 2013Assignee: Sony CorporationInventor: Hiromi Ogata