Patents by Inventor Hiromi Ogata

Hiromi Ogata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10263617
    Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: April 16, 2019
    Assignee: Sony Corporation
    Inventor: Hiromi Ogata
  • Publication number: 20170331472
    Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.
    Type: Application
    Filed: July 31, 2017
    Publication date: November 16, 2017
    Inventor: Hiromi Ogata
  • Patent number: 9735775
    Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: August 15, 2017
    Assignee: Sony Corporation
    Inventor: Hiromi Ogata
  • Publication number: 20160156349
    Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.
    Type: Application
    Filed: December 1, 2015
    Publication date: June 2, 2016
    Inventor: Hiromi Ogata
  • Patent number: 9252763
    Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: February 2, 2016
    Assignee: Sony Corporation
    Inventor: Hiromi Ogata
  • Publication number: 20150194955
    Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.
    Type: Application
    Filed: March 23, 2015
    Publication date: July 9, 2015
    Inventor: Hiromi Ogata
  • Patent number: 9058979
    Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: June 16, 2015
    Assignee: Sony Corporation
    Inventor: Hiromi Ogata
  • Patent number: 9024662
    Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: May 5, 2015
    Assignee: Sony Corporation
    Inventor: Hiromi Ogata
  • Patent number: 8890568
    Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: November 18, 2014
    Assignee: Sony Corporation
    Inventor: Hiromi Ogata
  • Publication number: 20140232448
    Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.
    Type: Application
    Filed: April 28, 2014
    Publication date: August 21, 2014
    Applicant: Sony Corporation
    Inventor: Hiromi Ogata
  • Publication number: 20140203330
    Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.
    Type: Application
    Filed: March 25, 2014
    Publication date: July 24, 2014
    Applicant: SONY CORPORATION
    Inventor: Hiromi Ogata
  • Patent number: 8742793
    Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: June 3, 2014
    Assignee: Sony Corporation
    Inventor: Hiromi Ogata
  • Patent number: RE45614
    Abstract: A semiconductor integrated circuit includes: a first voltage line on which a specific one of a power-supply voltage and a reference voltage appears; a second voltage line; a plurality of circuit cells each receiving power generated as a difference between a voltage appearing on the second voltage line and the other one of the power-supply voltage and the reference voltage; a plurality of switch transistors connected in parallel between the first and second voltage lines to serve as switch transistors including switch transistors each having different conducting-state resistances; and a switch conduction control section for controlling a transition of each of the switch transistors from a non-conducting state to a conducting state by turning on the switch transistors at separate points of time.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: July 14, 2015
    Assignee: Sony Corporation
    Inventors: Masahiro Igarashi, Tetsuo Motomura, Ryuji Kaneko, Makoto Fujiwara, Yoshinori Tanaka, Hiromi Ogata
  • Patent number: RE46997
    Abstract: A semiconductor integrated circuit includes: a first voltage line on which a specific one of a power-supply voltage and a reference voltage appears; a second voltage line; a plurality of circuit cells each receiving power generated as a difference between a voltage appearing on the second voltage line and the other one of the power-supply voltage and the reference voltage; a plurality of switch transistors connected in parallel between the first and second voltage lines to serve as switch transistors including switch transistors each having different conducting-state resistances; and a switch conduction control section for controlling a transition of each of the switch transistors from a non-conducting state to a conducting state by turning on the switch transistors at separate points of time.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: August 14, 2018
    Assignee: Sony Corporation
    Inventors: Masahiro Igarashi, Tetsuo Motomura, Ryuji Kaneko, Makoto Fujiwara, Yoshinori Tanaka, Hiromi Ogata
  • Patent number: RE47629
    Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: October 1, 2019
    Assignee: Sony Corporation
    Inventor: Hiromi Ogata
  • Patent number: RE48373
    Abstract: A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: December 29, 2020
    Assignee: Sony Corporation
    Inventor: Hiromi Ogata
  • Patent number: RE48694
    Abstract: A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: August 17, 2021
    Assignee: Sony Corporation
    Inventor: Hiromi Ogata
  • Patent number: RE48941
    Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: February 22, 2022
    Assignee: Sony Group Corporation
    Inventor: Hiromi Ogata
  • Patent number: RE49662
    Abstract: A semiconductor integrated circuit includes: a first voltage line on which a specific one of a power-supply voltage and a reference voltage appears; a second voltage line; a plurality of circuit cells each receiving power generated as a difference between a voltage appearing on the second voltage line and the other one of the power-supply voltage and the reference voltage; a plurality of switch transistors connected in parallel between the first and second voltage lines to serve as switch transistors including switch transistors each having different conducting-state resistances; and a switch conduction control section for controlling a transition of each of the switch transistors from a non-conducting state to a conducting state by turning on the switch transistors at separate points of time.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: September 19, 2023
    Assignee: Sony Group Corporation
    Inventors: Masahiro Igarashi, Tetsuo Motomura, Ryuji Kaneko, Makoto Fujiwara, Yoshinori Tanaka, Hiromi Ogata
  • Patent number: RE49986
    Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and dis-connection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: May 28, 2024
    Assignee: Sony Group Corporation
    Inventor: Hiromi Ogata