Patents by Inventor Hiromichi Suzuki

Hiromichi Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7081853
    Abstract: A mobile communication terminal comprises a first antenna element and a second antenna element. The first antenna element is arranged over the surface of the circuit substrate contained in the terminal cabinet, the surface being located remotest from the ear of the speaker on the phone. The second antenna element is arranged over the remotest surface and adapted to be pulled in the inside of the terminal cabinet or extended from the terminal cabinet, the second antenna element being electromagnetically coupled with one of the ends of the first antenna element in a state of being extended from the terminal cabinet.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: July 25, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Amano, Hiromichi Suzuki, Norimichi Chiba
  • Publication number: 20060138617
    Abstract: A semiconductor integrated circuit device is provided which includes a wire having a diameter equal to or less than 30 ?m, and a connected member molded by a resin. The connected member includes a metal layer including a palladium layer provided at a portion to which said wire is connected. A solder containing Pb as a main composition metal is provided at a portion outside a portion molded by the resin.
    Type: Application
    Filed: February 28, 2006
    Publication date: June 29, 2006
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Tsuyoshi Kaneda
  • Publication number: 20060125064
    Abstract: It is intended to improve the production yield of QFN (Quad Flat Non-leaded package) and attain a multi-pin structure. After a resin sealing member for sealing a semiconductor chip is formed by molding, a peripheral portion of the resin sealing member and a lead frame are both cut along a cutting line which is positioned inside (on a central side of the resin sealing member) of a line (molding line) extending along an outer edge of the resin sealing member, whereby the whole surface (upper and lower surfaces and both side faces) of each of leads exposed to side faces (cut faces) of the resin sealing member is covered with resin, thus preventing the occurrence of metallic burrs on the cut faces of the leads.
    Type: Application
    Filed: February 1, 2006
    Publication date: June 15, 2006
    Inventors: Fujio Ito, Hiromichi Suzuki, Hiroyuki Takeno, Hiroshi Shimoji, Fumio Murakami, Keiko Kurakawa
  • Patent number: 7038306
    Abstract: A semiconductor integrated circuit device is provided which includes a wire having a diameter equal to or less than 30 ?m, and a connected member molded by a resin. The connected member includes a metal layer including a palladium layer provided at a portion to which said wire is connected. A solder containing Pb as a main composition metal is provided at a portion outside a portion molded by the resin.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: May 2, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Tsuyoshi Kaneda
  • Patent number: 7019388
    Abstract: It is intended to improve the production yield of QFN (Quad Flat Non-leaded package) and attain a multi-pin structure. After a resin sealing member for sealing a semiconductor chip is formed by molding, a peripheral portion of the resin sealing member and a lead frame are both cut along a cutting line which is positioned inside (on a central side of the resin sealing member) of a line (molding line) extending along an outer edge of the resin sealing member, whereby the whole surface (upper and lower surfaces and both side faces) of each of leads exposed to side faces (cut faces) of the resin sealing member is covered with resin, thus preventing the occurrence of metallic burrs on the cut faces of the leads.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: March 28, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Fujio Ito, Hiromichi Suzuki, Hiroyuki Takeno, Hiroshi Shimoji, Fumio Murakami, Keiko Kurakawa
  • Publication number: 20060049499
    Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.
    Type: Application
    Filed: October 28, 2005
    Publication date: March 9, 2006
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
  • Patent number: 6989334
    Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: January 24, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
  • Publication number: 20060014321
    Abstract: Improvement in the reliability of a semiconductor device is aimed at. By heating a lead frame, after preparing a lead frame with a tape, until a resin molding is performed, at the temperature 160 to 300° C. (preferably 180 to 300° C.) for a total of more than 2 minutes in the atmosphere which has oxygen, crosslinkage density becoming high in resin of adhesives, a low molecular compound volatilizes and jumps out outside, therefore as a result, since a low molecular compound does not remain in resin of adhesives, the generation of copper migration can be prevented.
    Type: Application
    Filed: July 15, 2005
    Publication date: January 19, 2006
    Inventors: Fujio Ito, Hiromichi Suzuki, Akihiko Kameoka, Junpei Kusukawa, Yoshitaka Takezawa
  • Publication number: 20050263863
    Abstract: Miniaturization in a semiconductor device which has a chip part is attained. A QFP having the chip part includes a semiconductor chip, a plurality of inner leads arranged around the semiconductor chip, a sheet member which connects with the end part of the inner lead via insulating adhesive and which connects with the semiconductor chip via adhesive, a plurality of outer leads which are respectively integral with an inner lead, a plurality of wires which connect the pads of the semiconductor chip and a plurality of inner leads, respectively, and a bar lead arranged along the periphery of a plurality of inner leads in the domain between the semiconductor chip and the plurality of inner leads. In the domain between the semiconductor chip and a plurality of inner leads, the chip part which constitutes a surface mounting part is mounted on the bar lead, while being arranged beneath the wire.
    Type: Application
    Filed: May 31, 2005
    Publication date: December 1, 2005
    Inventors: Toshio Sasaki, Fujio Ito, Hiromichi Suzuki
  • Publication number: 20050258524
    Abstract: A manufacturing method of a semiconductor device including preparing a lead frame having a die pad, leads arranged around the die pad and a silver plating layer formed over a first portion of each of the leads, mounting a semiconductor chip over a main surface of the die pad with a rear surface of the chip fixed to the main surface of the die pad, electrically connecting electrodes of the chip with the leads through wires, forming a molding resin sealing the die pad, the first portion, the semiconductor chip, and the wires, and forming a lead-free solder plating layer over a second portion of each of the leads exposed from the molding resin. An area of the die pad is smaller than an area of the chip, and a part of the molding resin contacts with the rear surface of the chip exposed from the die pad.
    Type: Application
    Filed: June 17, 2005
    Publication date: November 24, 2005
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Kunihiko Nishi
  • Patent number: 6962836
    Abstract: A semiconductor device comprises a plurality of inner leads extending around a semiconductor chip, a tape substrate supporting the semiconductor chip and joined to respective end portions of the inner leads, wires connecting the inner leads and pads formed on a main surface of the semiconductor chip, a seal portion formed by resin-sealing the semiconductor chip and the wires, and a plurality of outer leads linking in a line with the inner leads and protruded from the seal portion to the exterior of four directions. A relationship between a length (a) of a shorter side of the semiconductor chip and a clearance (b) from the semiconductor chip, to a tip of the inner leads arranged at the farthest location from the semiconductor chip is a?2b. It is possible to attain a narrow pad pitch, and mount the semiconductor chip formed in a small size, and standardize the lead frame.
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: November 8, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki
  • Patent number: 6960823
    Abstract: To improve a reflow characteristic and realize leadlessness. A semiconductor device comprises a cross die pad which supports a semiconductor chip and in which an area of the region joined to the semiconductor chip is smaller than that of the outer size thereof being smaller than the rear surface of the semiconductor chip; wires connected to pads of the semiconductor chip; a plurality of inner leads which are arranged around the semiconductor chip and in which a silver plating layer is formed at a wire bonding area; molding resin for resin sealing the semiconductor chip; a plurality of outer leads exposed from the molding resin and in which a lead-free metallic layer is formed on a contact surface, wherein the flat surface size of the molding resin is formed to be equal to or less than 28 mm×28 mm and the thickness thereof is formed to be 1.4 mm or less, and thereby it is possible to improve a reflow characteristic and realize leadlessness.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: November 1, 2005
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Kunihiko Nishi
  • Publication number: 20050230793
    Abstract: A semiconductor device comprises a microcomputer chip, an SDRAM which is disposed alongside the microcomputer chip and is thinner than the microcomputer chip, a tub, a plurality of inner leads and outer leads, first wires that connect pads of the microcomputer chip and pads of the SDRAM, and second wires which connect the pads of the microcomputer chip and the inner leads and which are disposed so as to bridge over the SDRAM and are formed with loops at positions higher than loops of the first wires. An interface circuit for a memory bus is connected only between the chips, without connecting to external terminals, and is closed within a package. Therefore, pins can be utilized for other functions correspondingly and a multi-pin configuration can be achieved. Further, the cost of an SIP (semiconductor device) can be reduced owing to the adoption of a frame type.
    Type: Application
    Filed: April 15, 2005
    Publication date: October 20, 2005
    Inventors: Fujio Ito, Hiromichi Suzuki, Akihiko Kameoka, Noriaki Sakamoto
  • Patent number: 6943456
    Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: September 13, 2005
    Assignees: Hitachi Ulsi Systems Co., Ltd., Hitachi, Ltd.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
  • Publication number: 20050196903
    Abstract: A manufacturing method of a semiconductor device including preparing a lead frame having a die pad, leads arranged around the die pad and a silver plating layer formed over a first portion of each of the leads, mounting a semiconductor chip over a main surface of the die pad with a rear surface of the chip fixed to the main surface of the die pad, electrically connecting electrodes of the chip with the leads through wires, forming a molding resin sealing the die pad, the first portion, the semiconductor chip, and the wires, and forming a lead-free solder plating layer over a second portion of each of the leads exposed from the molding resin. An area of the die pad is smaller than an area of the chip, and a part of the molding resin contacts with the rear surface of the chip exposed from the die pad.
    Type: Application
    Filed: April 7, 2005
    Publication date: September 8, 2005
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Kunihiko Nishi
  • Publication number: 20050189627
    Abstract: A surface mounting method for mounting semiconductor devices suppresses solder peeling defects which tried to occur during mounting. The method used for mounting semiconductor devices includes a process for preparing the semiconductor devices by obtaining multiple terminals by exposing a section of each of multiple leads protruding from a rear side of the plastic casing, and forming a layer of solder by solidifying a molten solder material; a process for supplying a solder paste material to multiple electrodes on a printed circuit board; and a process for melting the solder paste of the multiple electrodes and connecting each of the multiple terminals with the multiple electrodes.
    Type: Application
    Filed: February 25, 2005
    Publication date: September 1, 2005
    Inventors: Fujio Ito, Hiromichi Suzuki, Takashi Miwa, Tokuji Toida
  • Publication number: 20050189629
    Abstract: A method for manufacturing a semiconductor device includes the steps of providing a semiconductor device of a surface mounted type in which the main surface of a chip mounting portion connected to a semiconductor chip is formed so as to be smaller than the main surface of the semiconductor chip, accommodating the semiconductor device into a non-moistureproof, e.g., flammable, packing, and shipping the packed semiconductor device. The non-moistureproof packing may have a moisture permeability of T T?1 g/m2/24 hr. The method may also include providing a second semiconductor device of a surface-mounted type in which the main surface of a chip mounting portion connected to a semiconductor chip is formed so as to be larger than the main surface of the semiconductor chip, moistureproof-packing the second semiconductor device, and shipping and packed second semiconductor device.
    Type: Application
    Filed: February 28, 2005
    Publication date: September 1, 2005
    Inventors: Fujio Ito, Hiromichi Suzuki, Tokuji Toida
  • Patent number: 6936333
    Abstract: A bulky sheet comprising a fiber aggregate formed by water needling of a fiber web is disclosed. The bulky sheet has a number of projections and depressions comprising the fiber aggregate. The projections and the depressions is formed both by rearrangement of the constituting fibers of the fiber aggregate by water needling of the fiber aggregate and by the multiple bending manner of the fiber aggregate along the thickness direction thereof. The projections and the depressions retains the shape thereof by themselves.
    Type: Grant
    Filed: February 13, 2001
    Date of Patent: August 30, 2005
    Assignee: Kao Corporation
    Inventors: Akihito Shizuno, Kenji Ishikawa, Kouji Machii, Hiromichi Suzuki
  • Publication number: 20050176171
    Abstract: A method of manufacturing a thin, small-sized, inexpensive, non-leaded, resin-sealed type semiconductor device is disclosed. A flexible tape having plural terminals peelably through a first adhesive in a product forming portion formed on a main surface of the tape is provided, a semiconductor element is fixed to the main surface of the tape peelably through a second adhesive, electrodes formed on the semiconductor element and the terminals are connected together through conductive wires, an insulating resin layer is formed in an area including the semiconductor element and the wires on the main surface of the tape to cover the semiconductor element and the wires, and the tape on a back surface of the insulating resin layer is peeled, allowing the terminals to be exposed to the back surface of the insulating resin layer. Exposed surfaces of the terminals are each formed by a gold layer.
    Type: Application
    Filed: April 7, 2003
    Publication date: August 11, 2005
    Inventors: Yoshinori Miyaki, Yoshihiko Shimanuki, Hiromichi Suzuki, Fujio Ito
  • Publication number: 20050153755
    Abstract: A mobile communication terminal of a portable telephone is housed in a casing having a first surface. A receiver section of the portable telephone capable of generating a voice is arranged on the first surface. A two-wavelength loop antenna arranged on a plane substantially parallel to the first plane and formed of a looped line having a right section and a left section that are in symmetry with respect to an imaginary vertical symmetric line is housed in the casing. A power supply point for supplying an electric power to the loop antenna is arranged in the vicinity of the intersection between the symmetric line and the looped line.
    Type: Application
    Filed: September 24, 2004
    Publication date: July 14, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiromichi Suzuki, Takashi Amano