Patents by Inventor Hiromichi Suzuki

Hiromichi Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050147488
    Abstract: To prevent semiconductor chips from adhering to the trays during transport, a method is employed which transports semiconductor chips in the following state. When trays provided with a plurality of accommodating portions having a recessed cross section for accommodating semiconductor chips on a main surface thereof are stacked in a plurality of stages, the semiconductor chips are accommodated in spaces defined by the accommodating portions formed over the main surface of the lower-stage tray and corresponding accommodating portions formed over the back surface of the upper-stage tray. Here, on bottom surfaces of the accommodating portions formed over the back surface of the upper-stage tray, isolated projections having a height which prevents the projections from coming into contact with the semiconductor chips are arranged in a scattered manner. In this way, it is possible to prevent the semiconductor chips from adhering to the back surface of the upper-stage tray.
    Type: Application
    Filed: December 9, 2004
    Publication date: July 7, 2005
    Inventors: Yoshihisa Matsubara, Hiromichi Suzuki, Wahei Kitamura, Kosho Akiyama, Seiji Kato
  • Publication number: 20050136218
    Abstract: A bulky sheet comprising a fiber aggregate formed by water needling of a fiber web is disclosed. The bulky sheet has a number of projections and depressions comprising the fiber aggregate. The projections and the depressions is formed both by rearrangement of the constituting fibers of the fiber aggregate by water needling of the fiber aggregate and by the multiple bending manner of the fiber aggregate along the thickness direction thereof. The projections and the depressions retains the shape thereof by themselves.
    Type: Application
    Filed: February 8, 2005
    Publication date: June 23, 2005
    Applicant: KAO CORPORATION
    Inventors: Akihito Shizuno, Kenji Ishikawa, Kouji Machii, Hiromichi Suzuki
  • Patent number: 6893898
    Abstract: A semiconductor device comprising a semiconductor chip with plural electrodes arranged on a main surface thereof, plural leads electrically connected respectively to the plural electrodes on the semiconductor chip, and a resin sealing body which seals the semiconductor chip and the plural leads, wherein the plural leads include first leads and second leads adjacent to the first leads, the first leads having first external connections exposed from a mounting surface of the resin sealing body and positioned near a side face of the resin sealing body, the second leads having second external connections exposed from the mounting surface of the resin sealing body and positioned closer to the semiconductor chip with respect to the first external connections. The first and second leads are fixed to the semiconductor chip. The semiconductor device is suitable for a multi-pin structure and the manufacturing yield thereof is improved.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: May 17, 2005
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Fujio Ito, Hiromichi Suzuki
  • Patent number: 6891253
    Abstract: Arrangements are provided to effectively prevent wire disconnection generated due to an increase of heat applied to a semiconductor integrated circuit device. The semiconductor integrated circuit device is structured such that a metal layer containing a Pd layer is provided in a portion to which a connecting member having a conductivity is connected, and an alloy layer having a melting point higher than that of an Sn—Pb eutectic solder and containing no Pb as a main composing metal is provided outside a portion molded by a resin. Further, a metal layer in which a thickness in a portion to which the connecting member having the conductivity is adhered is equal to or more than 10 ?m is provided in the connecting member.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: May 10, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Tsuyoshi Kaneda
  • Publication number: 20040262752
    Abstract: A semiconductor chip has a plurality of electrodes arranged along one side thereof; a plurality of leads arranged outside the one side thereof in the same direction as the above side; a plurality of bonding wires electrically connecting the electrodes to the leads; and a resin sealing member sealing the semiconductor chip, the leads and the bonding wires. The leads include first leads, each having a terminal portion which is located on the side face of the resin sealing member and exposed from the rear surface thereof, and second leads, each having a terminal portion which is located on the inner side of the terminal portions of the first leads and exposed from the rear surface of the resin sealing member. The first leads and the second leads are arranged alternately. The plurality of bonding wires are connected to the respective leads on the inner side of the terminal portions of the first leads.
    Type: Application
    Filed: June 4, 2004
    Publication date: December 30, 2004
    Inventors: Fujio Ito, Hiromichi Suzuki, Takafumi Konno, Tsugio Umehara
  • Publication number: 20040245607
    Abstract: A semiconductor integrated circuit device is provided which includes a wire having a diameter equal to or less than 30 &mgr;m, and a connected member molded by a resin. The connected member includes a metal layer including a palladium layer provided at a portion to which said wire is connected. A solder containing Pb as a main composition metal is provided at a portion outside a portion molded by the resin.
    Type: Application
    Filed: July 14, 2004
    Publication date: December 9, 2004
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Tsuyoshi Kaneda
  • Publication number: 20040232527
    Abstract: A semiconductor device is disclosed which is improved in the mounting reliability and which has external terminals formed by exposing portions of leads from a back surface of a resin sealing member. End portions on one side of the leads are fixed to a back surface of a semiconductor chip, and portions of the leads positioned outside the semiconductor chip are connected with electrodes formed on the semiconductor chip through wires.
    Type: Application
    Filed: May 20, 2004
    Publication date: November 25, 2004
    Inventors: Fujio Ito, Hiromichi Suzuki
  • Patent number: 6803258
    Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w<t and p≦1.2t, with the inner leads secured to the heat radiation plate. The heat radiation plate has slits made therein to form radially shaped heat propagation paths between a semiconductor chip mounting area and the inner leads.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: October 12, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Fujio Ito, Hiroaki Tanaka, Hiromichi Suzuki, Tokuji Toida, Takafumi Konno, Kunihiro Tsubosaki, Shigeki Tanaka, Kazunari Suzuki, Akihiko Kameoka
  • Publication number: 20040181938
    Abstract: Clean accommodation and carrying of semiconductor devices are to be attained. A stack type tray is used which comprises a base portion 1d with plural pockets formed therein in a matrix shape and side walls formed along peripheral edges of the base portion. In the tray is buried an electronic tag which is constituted by a mu-chip having memory with non-contact recognizable information stored therein. Information pieces such as ID, manufacturer's name and product number of the tray, as well as product name, quantity and lot number of an object to be accommodated, are stored in the mu-chip of the electronic tag, and by accommodating a to-be-accommodated object in the tray equipped with the mu-chip and carrying it, the generation of dust can be prevented because paper label is not used.
    Type: Application
    Filed: February 4, 2004
    Publication date: September 23, 2004
    Applicants: Renesas Technology Corp, Hitachi Transport System, Ltd.
    Inventors: Hiromichi Suzuki, Wahei Kitamura, Tokuji Toida, Toshimasa Shirai
  • Patent number: 6791182
    Abstract: At least a part of the inner leads 1a of a lead frame 1 is covered with a plating for a metallic fine wire connection, at least the entire portion where the lead frame 1 joins with the adhesive layer 2 is covered by at least one metal or alloy thereof different from the metallic fine wire connecting use plating. The metal or alloy is selected from the group consisting of gold, platinum, iridium, rhodium, palladium, ruthenium, indium, tin, molybdenum, tungsten, gallium, zinc, chromium, niobium, tantalum, titanium and zirconium. Thereby, generation of defects, such as leakage and shorting, due to ion migration can be prevented.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: September 14, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Junpei Kusukawa, Ryozo Takeuchi, Toshiaki Ishii, Hiromichi Suzuki, Fujio Ito, Takafumi Nishita, Akihiko Kameoka, Masaru Yamada
  • Patent number: 6788259
    Abstract: A flexible substrate having a meandering antenna element and a matching circuit formed thereon is wound within an antenna cap and mounted on a terminal body. A rod-like antenna is arranged extensible within the flexible substrate. If the rod-like antenna is withdrawn, a linear antenna element is coupled by a capacitive coupling with the matching circuit formed on the flexible substrate. Also, if the rod-like antenna is returned into the terminal body, the capacitive coupling between the linear antenna element and the matching circuit is released, and the meandering antenna element is coupled by a capacitive coupling with the matching circuit on the flexible substrate.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: September 7, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Amano, Norimichi Chiba, Hisao Iwasaki, Hiromichi Suzuki
  • Patent number: 6780679
    Abstract: The mounting reliability of a QFN (Quad Flat Non-leaded package) having a large number of pins is improved, and also the manufacturing cost of the QFN having a large number of pins is reduced. A die pad, on which a semiconductor die is mounted, is arranged at the center of a plastic package constituting a package of the QFN. A plurality of leads are arranged around the die pad so as to surround the die pad. Lead tips on one side near the semiconductor die are electrically connected to bonding pads on a main surface of the semiconductor die via gold wires, and lead tips on the other side terminate at a side surface of the plastic package. On a rear surface of the plastic package, external connection terminals formed by pressing and bending the respective parts of the plurality of leads protrude to the outside, and a solder layer is formed on each surface of the terminals.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: August 24, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Fujio Ito, Hiromichi Suzuki
  • Publication number: 20040159922
    Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.
    Type: Application
    Filed: February 13, 2004
    Publication date: August 19, 2004
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
  • Patent number: 6777262
    Abstract: In order to suppress defective lead forming and defective mounting, a semiconductor device comprises a sealing body which has a square planar shape, a semiconductor chip which lies within the sealing body, and a plurality of leads which are electrically connected with electrodes of the semiconductor chip, which extend inside and outside the sealing body and which are arrayed along latera of the sealing body, wherein an outer lead portion of each of the leads is such that a root part which protrudes out of the sealing body is formed at a lead width being equal to or greater than a lead thickness, and that a mounting part which joins to the root part through an intermediate part is formed at a lead width being less than the lead thickness.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: August 17, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki
  • Publication number: 20040124506
    Abstract: It is intended to improve the production yield of QFN (Quad Flat Non-leaded package) and attain a multi-pin structure. After a resin sealing member for sealing a semiconductor chip is formed by molding, a peripheral portion of the resin sealing member and a lead frame are both cut along a cutting line which is positioned inside (on a central side of the resin sealing member) of a line (molding line) extending along an outer edge of the resin sealing member, whereby the whole surface (upper and lower surfaces and both side faces) of each of leads exposed to side faces (cut faces) of the resin sealing member is covered with resin, thus preventing the occurrence of metallic burrs on the cut faces of the leads.
    Type: Application
    Filed: December 9, 2003
    Publication date: July 1, 2004
    Applicants: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Fujio Ito, Hiromichi Suzuki, Hiroyuki Takeno, Hiroshi Shimoji, Fumio Murakami, Keiko Kurakawa
  • Publication number: 20040126932
    Abstract: A method of manufacturing a semiconductor device is provided including preparing a lead frame having a plurality of leads, wherein the lead widths of the lead tips are smaller than the lead thickness of the tips. A plate is also prepared having a first portion and second portion on a main surface thereof, the second portion being located at the outer periphery of said first portion. A semiconductor chip having a semiconductor element and a plurality of electrodes is fastened to the first portion of the plate and the lead tips are fastened on the second portion of the plate. Bonding wires are then formed to electrically connect the lead tips and the electrodes of the semiconductor chip, and then the lead tips, the plate, the semiconductor chip and the bonding wires are sealed with a molding member.
    Type: Application
    Filed: December 15, 2003
    Publication date: July 1, 2004
    Inventors: Fujio Ito, Hiroaki Tanaka, Hiromichi Suzuki, Tokuji Toida, Takafumi Konno, Kunihiro Tsubosaki, Shigeki Tanaka, Kazunari Suzuki, Akihiko Kameoka
  • Publication number: 20040089923
    Abstract: Attaining improvement of the reliability and standardization of the lead frame.
    Type: Application
    Filed: August 21, 2003
    Publication date: May 13, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki
  • Publication number: 20040051167
    Abstract: A semiconductor device comprises a plurality of inner leads extending around a semiconductor chip, a tape substrate 5 supporting the semiconductor chip and joined to respective end portions of the inner leads, wires connecting the inner leads and pads formed on a main surface of the semiconductor chip, a seal portion formed by resin-sealing the semiconductor chip and the wires, and a plurality of outer leads linking in a line with the inner leads and protruded from the seal portion to the exterior of four directions. A relationship between a length (a) of a shorter side of the semiconductor chip and a clearance (b) from the semiconductor chip, to a tip of the inner leads arranged at the farthest location from the semiconductor chip is a 2b. It is possible to attain a narrow pad pitch, and mount the semiconductor chip formed in a small size, and standardize the lead frame.
    Type: Application
    Filed: August 21, 2003
    Publication date: March 18, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki
  • Publication number: 20040046699
    Abstract: A mobile communication terminal comprises a first antenna element and a second antenna element. The first antenna element is arranged over the surface of the circuit substrate contained in the terminal cabinet, the surface being located remotest from the ear of the speaker on the phone. The second antenna element is arranged over the remotest surface and adapted to be pulled in the inside of the terminal cabinet or extended from the terminal cabinet, the second antenna element being electromagnetically coupled with one of the ends of the first antenna element in a state of being extended from the terminal cabinet.
    Type: Application
    Filed: March 13, 2003
    Publication date: March 11, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi Amano, Hiromichi Suzuki, Norimichi Chiba
  • Patent number: 6692989
    Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: February 17, 2004
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems, Co., Ltd.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi