Abstract: A semiconductor memory device comprising memory cells arranged in a matrix with plural pairs of bit lines to be column addressed and connected to sense amplifiers, and word lines to be row addressed and divided into divisional word lines. Output signals of sense amplifiers selected by the column addressing are transferred to respective data lines. The divisional word lines are time-sequentially activated corresponding to the row addressing with the activated states of any two sequential divisional word lines overlapped for a fractional time of the full activation time. The sense amplifiers are grouped into plural groups with respective common column addresses. Each group of sense amplifiers have their outputs to be applied to respective data lines connected to a serial/parallel converter.

Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Abstract: There are provided a MIS transistor having a substrate portion, a gate, a source, and a drain, a back-bias generator to be applied to the substrate portion of the MIS transistor, and a resistor interposed between the substrate portion of the MIS transistor and the back-bias generator so that the potential between the both ends thereof changes in a range from one value in the active mode to the other value in the standby mode of the MIS transistor. In the MIS transistor, the back bias is self-regulated so that it approaches to zero in the active mode, while it moves away from zero in the standby mode. Consequently, the threshold voltage is reduced in the active mode due to the back bias approaching to zero, so that higher-speed operation is performed. On the other hand, off-state leakage is suppressed in the standby mode due to the back bias moving away from zero. Thus, it becomes possible to constitute a semiconductor apparatus which operates at high speed with low power consumption.

Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Abstract: A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.

Abstract: In a synchronous DRAM required to be capable of performing high-speed consecutive operations in synchronism with a clock signal, a DBI-line pair is connected between a DQ-line pair and an RDB-line pair, and pipeline operation whose single cycle time is divided into four periods is employed.

Abstract: In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Abstract: N-piece redundant address comparing circuits are individually composed of impedance converting circuits, so that information using redundancy is transmitted as an impedance value. Consequently, even though the N becomes larger as the capacity of a memory becomes larger, a signal line having large capacitance and the node of a redundant judging circuit are not charged or discharged. A high-speed operation can be realized without being affected by the capacitance of the signal line or by the capacitance of the node of the redundant judging circuit.

Abstract: An external power supply voltage V.sub.CC is applied to a peripheral circuit as a first internal power supply voltage V.sub.PERI. A power supply voltage control circuit outputs a voltage control signal V.sub.SIG of a high logic level if V.sub.CC is not greater than a low limit voltage V.sub.0L in a voltage range specified by VCC recommended operating conditions, otherwise it outputs V.sub.SIG of a low logic level. A power supply circuit applies a second internal power supply voltage V.sub.W and a third internal power supply voltage V.sub.WORD to a memory cell section. V.sub.W is equal to V.sub.PERI if V.sub.SIG is HIGH, while on the other hand V.sub.W is a voltage as a result of boosting V.sub.PERI. V.sub.WORD is a voltage as a result of boosting VW to a further extent. A row decoder sends out V.sub.W onto an enable signal line of a row of sense amplifiers, and V.sub.WORD onto a word line of a memory cell array so that V.sub.W becomes a high-logic-level data write voltage to a memory cell.

Abstract: A semiconductor integrated circuit contains a plurality of programmable circuits each including a plurality of fuses and a first transistor which has a gate subjected to an address decoded signal, a drain connected to first ends of the fuses, and a source connected to a common precharge node. The address decoded signal results from decoding a first portion of an address signal for access to memory cells. The sources of the first transistors in the respective programmable circuits are connected to the common precharge node. A plurality of second transistors have gates subjected to a second portion of the address signal, sources connected to a first power supply line, and drains connected to second ends of the fuses in each of the programmable circuits respectively. The second portion of the address signal differs from the first portion of the address signal.

Abstract: An improved arrangement for refreshing a semiconductor memory device comprising a plurality of memory blocks is disclosed. In the memory device, word lines of all memory blocks are commonly controlled by one controller. One of the memory blocks is selected to be subject to the write/read operation. The refresh is performed in the remaining memory blocks while the selected memory block is written or read. The period of time required for the refresh can be decreased.

Abstract: A semiconductor memory includes a writing circuit for dividing data continuously supplied to a serial data input circuit into a plurality of bits, a serial data output circuit for continuously providing data read out a plurality of bits a a time by a reading circuit, a memory cell array including a column decoder and a row decoder, column and row address buffers for instructing addresses for a plurality of bits at a time to the respective column and row decoders, an address generator, and a circuit provided between the address generator and column decoder and including a read column address generator, a write column address generator and a column address control circuit for switching read and write column address generated from the read and write column address generators, wherein address identity data are simultaneously inputted and outputted through switching of internal column addresses for reading and writing.

Abstract: Through the step number control transfer gate activated by the step number control signal, the input data is sent into a specific transfer step of the shift register, and the data transferred from the specific transfer step is delivered from the output step. By selecting an arbitrary step number control transfer gate, the input transfer step is varied without changing the output step to change to an arbitrary data delay length. Therefore, only by increasing the driving capacity of the driver of the input data, a shift register short in delay time, small in increase of integration area, and low in power consumption will be obtained.