Abstract: A transport/storage cask for a radioactive material has an inner shell, an outer shell and a circular gamma ray shielding layer and a circular neutron shielding layer both of which are placed between the inner shell and the outer shell. The gamma ray shielding layer is formed by aligning a plurality of gamma ray shielding blocks composed of lead in a block shape in the circumferential direction. The entire gamma ray shielding block in the axial direction is covered with a copper tube having a higher elasticity limit than the gamma ray shielding block. In the above transport/storage cask, the gamma ray shielding layer composed of lead or a lead alloy is not easily deformed.

Abstract: An electrical fuse determination circuit that can speedily and reliably incorporate an electrical fuse data and improve a reliability of electrical fuse device, includes a first electrical fuse device of which one end connects with a higher voltage, a second electrical fuse device of which one end connects with a lower voltage, a set portion that puts one of the first electrical fuse device and the second electrical fuse device in a conductive state, and a determination portion that determines a voltage level of a predetermined contact point connecting the other end of the first electrical fuse device and the other end of the second electrical fuse device.

Abstract: A structure of solder joint structure formed of zinc-based lead-free solder having excellent characteristics is disclosed. Between a first lead-free solder layer and a soldering pad, the following layers are formed: a tin-copper alloy layer formed on the pad; a first alloy layer formed of second lead-free layer of which main ingredients are tin and silver; and a second alloy layer formed between the first alloy layer and the first lead-free solder. This structure allows forming the solder joint structure formed of zinc-based lead-free solder having high joint strength.

Abstract: A structure of solder joint structure formed of zinc-based lead-free solder having excellent characteristics is disclosed. Between a first lead-free solder layer and a soldering pad, the following layers are formed: a tin-copper alloy layer formed on the pad; a first alloy layer formed of second lead-free layer of which main ingredients are tin and silver; and a second alloy layer formed between the first alloy layer and the first lead-free solder. This structure allows forming the solder joint structure formed of zinc-based lead-free solder having high joint strength.

Abstract: A process for preparing a compound (5a) represented by the following formula: wherein R1 and R2 each independently represent hydrogen, C1-4 alkyl, etc. and A represents cyanophenyl, etc., characterized by reacting a compound (3a) represented by the following formula: wherein R1 and R2 have the same definitions as above, with a compound represented by the formula A—SO2Cl, wherein A has the same definition as above, in the presence of a base, in a mixed solvent of water and C1-6 alkyl acetate.

Abstract: The present invention provides a preventive or therapeutic agent for diabetes mellitus and diabetic complications, which is a new type based on an adenosine A2 receptor antagonist action. That is, it provides a novel condensed imidazole compound which has an adenosine A2 receptor antagonist action, is effective for preventing or treating diabetes mellitus and diabetic complications, and is represented by the formula (I); (wherein R1 represents e.g. an amino group which may be substituted with an alkyl group; R2 represents e.g. hydrogen atom, an alkyl group, a cycloalkyl group or an alkyl group, alkenyl group or alkynyl group which may be substituted with hydrox etc.; R3 represents e.g. an optionally substituted alkyl group, alkenyl group, alkynyl group, aryl group, heteroaryl group, pyridinone group, pyrimidinone group or piperadinone group; Ar represents e.g.

Abstract: A structure of solder joint structure formed of zinc-based lead-free solder having excellent characteristics is disclosed. Between a first lead-free solder layer and a soldering pad, the following layers are formed: a tin-copper alloy layer formed on the pad; a first alloy layer formed of second lead-free layer of which main ingredients are tin and silver; and a second alloy layer formed between the first alloy layer and the first lead-free solder. This structure allows forming the solder joint structure formed of zinc-based lead-free solder having high joint strength.

Abstract: A spare address conversion circuit makes an address assignment to spare sub word lines different from the address assignment to normal sub word lines between a mode of data writing and a mode of data reading. Data are written such that opposite data patterns are stored in spare word lines before and after address conversion. When a multi-selection occurs, there is data collision on the corresponding bit lines, so that the multi-selection can be detected without fail.

Abstract: A spare address conversion circuit makes an address assignment to spare sub word lines different from the address assignment to normal sub word lines between a mode of data writing and a mode of data reading. Data are written such that opposite data patterns are stored in spare word lines before and after address conversion. When a multi-selection occurs, there is data collision on the corresponding bit lines, so that the multi-selection can be detected without fail.

Abstract: The semiconductor memory device in accordance with the present invention allows evaluation of input/output terminal dependency of noise characteristic at the time of data output, it has a normal operation mode and a test mode, and includes a plurality of output buffers and selecting means for selectively activating at least one output buffer among the plurality of output buffers in the test mode.

Abstract: The semiconductor memory device in accordance with the present invention allows evaluation of input/output terminal dependency of noise characteristic at the time of data output, it has a normal operation mode and a test mode, and includes a plurality of output buffers and selecting means for selectively activating at least one output buffer among the plurality of output buffers in the test mode.

Abstract: The semiconductor memory device in accordance with the present invention allows evaluation of input/output terminal dependency of noise characteristic at the time of data output, it has a normal operation mode and a test mode, and includes a plurality of output at buffers and selecting means for selectively activating at least one output buffer among the plurality of output buffers in the test mode.

Abstract: An external terminal and an internal power supply node to an internal circuit are connected via first and second transistors. In a test operation mode, the first and second transisters are turned on and potential is accordingly supplied to the internal circuit from the terminal. In a normal operation mode, a third transistor placed between the terminal and the gate of the first transistor is turned on so that the gate of the first transistor is coupled to the external terminal and the second transistor is turned off. Undershoot to the terminal is not transmitted to the inside since the first transistor is turned off.

Abstract: An output buffer includes an NAND circuit, a first N channel MOS transistor connected between a power supply node and an output node, a second N channel MOS transistor connected between the output node and a ground node, the first to third drive circuits, and a delay circuit. The power supply voltage is first supplied to the gate of the second N channel MOS transistor by the second drive circuit. After a delay time delayed by the delay circuit has passed, boosted voltage is supplied to the gate of the second N channel MOS transistor by the third drive circuit. Accordingly, the output buffer is not influenced by the ringing and the pull-down characteristic improves.

Abstract: In an SDRAM, when a spare column selection line is not used, access to a column selection line is started at a first time at which complementary column address signals are defined, and access to the column selection line is stopped until a second time at which the level of a redundant column decoder activation signal is defined when the spare column selection line is used. Compared with the case in which access to the column selection line is always stopped until the second time, the access speed is increased.

Abstract: A cask for a radioactive material has a single gamma ray and neutron shielding layer disposed on the outside of a vessel body, and the shielding layer is formed of the compact of a mixture of lead and a metal hydride dispersed therein. This cask can exhibit an excellent shielding effect according to the balance of radiation source intensity between gamma rays and neutrons, and can be made more compact.

Abstract: A detect circuit receives a write enable signal, a column address strobe signal and an output control signal to predetect a mode in which data is input from an input/output terminal. While a substrate potential generation circuit normally operates, a substrate potential holding circuit also operates when the detect circuit detects the mode in which data is input, so that biasing capability of a substrate potential generating portion is increased before the data is actually input from the input/output terminal.

Abstract: A compression reading switch circuit is provided between a data equality/inequality determination circuit and compressed one data input/output terminal in a DRAM. In the I/O compression mode, desired data can be read out among output data DOT from the determination circuit and read data D01-D04 thereby specifying a defective memory cell among four memory cells.

Abstract: A semiconductor integrated circuit device includes a test mode circuit for generating a fuse blow test mode activation signal according to a signal applied to a predetermined terminal, a pass/fail confirmation circuit including a fuse element and providing a signal of a logic level according to a conduction/non-conduction state of this fuse element when the fuse blow test mode activation signal from the test mode circuit is active, and an output conversion circuit for converting an output signal of the pass/fail confirmation circuit into a signal observable at a predetermined external terminal. The fuse element included in the pass/fail confirmation circuit is blown out by a laser only when the semiconductor integrated circuit device is determined to be an acceptable product at the test of the wafer level. After packaging, determination of whether there is a cut off failure in any internal fuse element can easily be made in non-destructive manner.

Abstract: A negative power supply circuit is connected via an NMOS transistor to a node receiving ground potential in a sense amplifier. A one shot pulse generation circuit provides a one shot pulse signal to the gate of the NMOS transistor. The NMOS transistor is turned on when a one shot pulse signal is applied to connect the negative power supply circuit to the node. This causes the potential of the node to be lowered to a negative potential. As a result, increase in the potential at the ground side of the sense amplifier caused by an interconnection resistance in the ground interconnection is suppressed. Therefore, variation in the potential received by the sense amplifier due to interconnection resistance can be suppressed.