Patents by Inventor Hiroshi Furukawa

Hiroshi Furukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7929413
    Abstract: A transmission system capable of obtaining an effect of orthogonality among time block codes and an effect of path diversity on a distorted channel is provided. In the transmission system including: a transmitter device transmitting an information signal S[n] multiplied by a code, the code being a time block code constituted by a plurality of time series symbols, the transmitter device multiplying the information signal by a plurality of the time block codes, respectively, multiplexing multiplication results on a time axis and transmitting multiplexed signals; and a receiver device including a reception filter, if an impulse response matrix of a channel is a matrix H, a characteristic of the reception filter is set to be represented by a complex conjugate transpose matrix HH to the matrix H and each of the time block codes is set by an eigen code E_I[n] represented by an eigen vector of a matrix HHH representing a coupled system in which the channel is coupled to the reception filter.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: April 19, 2011
    Assignee: Kyushu University, National University Corporation
    Inventor: Hiroshi Furukawa
  • Publication number: 20110079930
    Abstract: A method of butting and connecting a first optical fiber and a second optical fiber in an optical connector comprises placing said optical connector that holds said first optical fiber in wherein an optical fiber connection tool; mounting said optical fiber holder on a holder mounting base of a front end bevel processing tool; processing a front end face of said second optical fiber such that said front end face of said second optical fiber is beveled relative to the surface perpendicular to the optical fiber axis direction; transferring said optical fiber holder to said holder support base; and moving said optical fiber holder toward said optical connector along said guide part, and butting and connecting the beveled front end face of said second optical fiber to the front end face of said first optical fiber such that their bevel directions are aligned.
    Type: Application
    Filed: December 10, 2010
    Publication date: April 7, 2011
    Applicant: Fujikura Ltd.
    Inventors: Daigo SAITO, Kazuhiro Takizawa, Hiroshi Furukawa, Serin Khee Yen Tan, Quang Minh Ngo
  • Patent number: 7912493
    Abstract: A transmission power control technique allowing stable and reliable signal transmission in soft handover is disclosed. Each of the base stations involved in soft handover measures an amount of loss of the base station selection signal. When the amount of loss of the base station selection signal exceeds a threshold, the transmission power of the downlink signal is not set to the minimum level but to the normally controlled level. Further, a transmission power update timing of each base station is determined so that the downlink signal received at the mobile station changes in transmission power at a predetermined timing synchronized with that of other base stations.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: March 22, 2011
    Assignee: NEC Corporation
    Inventor: Hiroshi Furukawa
  • Patent number: 7908453
    Abstract: A semiconductor device includes a plurality of memories, a sequencer which outputs configuration information, and a memory reconfiguring circuit which reconfigures the memory area in accordance with the configuration information supplied from the sequencer. Since the memory reconfiguring circuit dynamically changes the allocation of the memories, it is possible to reconfigure the memory configuration and freely change the memory size in accordance with the purpose of use.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: March 15, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tetsuo Kawano, Hiroshi Furukawa, Ichiro Kasama, Kazuaki Imafuku, Toshiaki Suzuki, Miyoshi Saito
  • Publication number: 20100332795
    Abstract: A computer system includes a central processing unit, a random-access-memory interface, a random-access memory in which addresses are allocated in an address space of the random-access-memory interface and a reconfigurable arithmetic device whose arithmetic function is capable of being dynamically changed in accordance with configuration data. The reconfigurable arithmetic device includes input terminals, output terminals, a plurality of processor elements that perform individual arithmetic processes in synchronization with a clock, an inter-processor-element network which connects the input terminals and the output terminals to input ports and output ports of the plurality of processor elements, a random-access memory built into the reconfigurable arithmetic device and a control unit that sets the plurality of processor elements and the inter-processor-element network.
    Type: Application
    Filed: June 7, 2010
    Publication date: December 30, 2010
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hiroshi FURUKAWA, Ichiro Kasama
  • Patent number: 7822888
    Abstract: An operation apparatus includes a sequencer controlling states of a plurality of operation devices and a configuration memory storing therein configuration information as setting information for each state in the operation device. In the operation apparatus, a path which requires a data buffer and another path which requires no such a data buffer are provided for inputting data to the operation device, a data buffer control part is provided for controlling selection from these two paths and operation of the data buffer, and contents of path selection and operation control of the data buffer carried out by the data buffer control part are set according to the configuration information.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: October 26, 2010
    Assignee: Fujitsu Limited
    Inventors: Miyoshi Saito, Hisanori Fujisawa, Ichiro Kasama, Tetsuo Kawano, Kazuaki Imafuku, Hiroshi Furukawa, Shiro Uriu, Mitsuharu Wakayoshi
  • Patent number: 7774580
    Abstract: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: August 10, 2010
    Assignee: Fujitsu Limited
    Inventors: Miyoshi Saito, Hisanori Fujisawa, Hideki Yoshizawa, Tetsu Tanizawa, Ichiro Kasama, Tetsuo Kawano, Kazuaki Imafuku, Hiroshi Furukawa, Shiro Uriu, Mitsuharu Wakayoshi
  • Patent number: 7761489
    Abstract: A managing computer is connected to object computers, the managing computer being connected to the object computers and the storage which is connected to the object computers for managing the object computers and the storage. The managing computer includes an interface for receiving volume managing information relating to storage areas in the storage, file sharing information relating to file sharing in the storage which is provided by the object computers and storage managing information relating to the storage, and a control unit which specifies the object computers or the storage to be preset controlled according to the volume managing information, the file sharing information and the storage managing information for managing the object computers and the storage by instructing the specified object computers or the specified storage to carry out the preset control.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: July 20, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Furukawa, Yasunori Kaneda
  • Patent number: 7757279
    Abstract: In a storage subsystem which is connected to an IP network, by excluding an improper packet, security is heightened, and a performance of communication to a logical unit of storage subsystem is maintained and secured. In the storage subsystem, a function which carries out filtering of a packet other than an iSCSI packet is provided. With respect to only the packet passed through the function, its accessibility to the logical unit is filtered. Also, traffic of all received packets, and a traffic lob of a packet judged to be discarded by the above filtering is recorded. By using this information, controlling such as a cut-off process of improper communication, QoS securement for normal communication and so on, are carried out.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: July 13, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Furukawa, Esutaro Akagawa
  • Patent number: 7754585
    Abstract: A method of subjecting a silicon wafer doped with boron to a heat treatment in an argon atmosphere, wherein the argon atmosphere is replaced with a hydrogen atmosphere or a mixed gas of an argon gas and a hydrogen gas in a proper fashion, to thereby uniformize a boron concentration in the thickness direction of the surface layer of the silicon wafer doped with boron.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: July 13, 2010
    Assignee: Sumco Techxiv Corporation
    Inventors: Yuji Sato, Shirou Yoshino, Hiroshi Furukawa, Hiroyuki Matsuyama
  • Patent number: 7734896
    Abstract: A reconfigurable integrated circuit device which converts an arbitrary calculation state dynamically, based on configuration data, includes a plurality of processor elements, each of which has an input terminal, an output terminal, a plurality of arithmetic units which are provided in parallel and each of which performs calculation processing in synchronous with a clock signal, and an intra-processor network which connects them in an arbitrary state; and an inter-processor network which connects between processor elements in an arbitrary state. Based on configuration data, the intra-processor network is reconfigurable to a desired connection state, and further, based on the configuration data, the inter-processor network is reconfigurable to a desired connection state.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: June 8, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Hiroshi Furukawa
  • Publication number: 20100067365
    Abstract: A transmission system capable of obtaining an effect of orthogonality among time block codes and an effect of path diversity on a distorted channel is provided. In the transmission system including: a transmitter device transmitting an information signal S[n] multiplied by a code, the code being a time block code constituted by a plurality of time series symbols, the transmitter device multiplying the information signal by a plurality of the time block codes, respectively, multiplexing multiplication results on a time axis and transmitting multiplexed signals; and a receiver device including a reception filter, if an impulse response matrix of a channel is a matrix H, a characteristic of the reception filter is set to be represented by a complex conjugate transpose matrix HH to the matrix H and each of the time block codes is set by an eigen code E_I[n] represented by an eigen vector of a matrix HHH representing a coupled system in which the channel is coupled to the reception filter.
    Type: Application
    Filed: June 12, 2007
    Publication date: March 18, 2010
    Applicant: KYUSHU UNIVERSITY, NATIONAL UNIVERSITY CORPORATION
    Inventor: Hiroshi Furukawa
  • Publication number: 20090271461
    Abstract: There is provided a semiconductor integrated circuit including: a plurality of first logic blocks which are reconfigurable, the plurality of first logic blocks inputting data of a first bit width and performing computation; a first network connecting the plurality of first logic blocks in a dynamically reconfigurable manner; a plurality of second logic blocks inputting data of a second bit width different from the first bit width and performing computation; a second network connected to outputs of the plurality of second logic blocks; and a third network connecting a carry bit output of a computing unit included in the first logic block to an input of a computing unit included in the second logic block in a dynamically reconfigurable manner.
    Type: Application
    Filed: December 11, 2008
    Publication date: October 29, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Hiroshi FURUKAWA
  • Patent number: 7590081
    Abstract: A radio network can select a route of minimum path loss among entire relay routes and can set the relay route so as to satisfactorily resist interference. The radio network has a core node connected to a wired network, relay nodes each relaying at least one of a down-link data packet transmitted from the core node and an up-link data packet directed toward the core node, and a terminal station capable of transmission and reception of data packets with both the core node and the relay node. The relay node has total path loss optimized to be minimum between relay nodes included in a relay route of the data packet or between the relay node and the core node or both.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: September 15, 2009
    Assignee: NEC Corporation
    Inventors: Hiroshi Furukawa, Morihisa Momona, Koichi Ebata
  • Patent number: 7580963
    Abstract: A semiconductor device includes a configuration memory for storing configuration data, an arithmetic unit whose circuit configuration can be reconfigured in accordance with the configuration data, and a fixed value memory for storing fixed value data to be supplied to the arithmetic unit. Since the configuration data and fixed value data to be supplied to the arithmetic unit are stored in the different memories, no data area for storing the fixed value data need be set in the configuration memory. This makes it possible to supply a predetermined fixed value to the arithmetic unit by storing only information for reading out fixed value data from the fixed value memory.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: August 25, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Tetsuo Kawano, Hiroshi Furukawa, Ichiro Kasama, Kazuaki Imafuku, Toshiaki Suzuki
  • Publication number: 20090172144
    Abstract: An ID collection and management apparatus which manages identifiers of computers in a computer system including said computers and a storage system which provides said computers with a storage volume, including: a first ID acquisition unit which acquires first IDs which are IDs of a data port for said computers to transmit/receive data with said storage volume; a second ID acquisition unit which acquires second IDs to be recognized as the IDs of said computers by said storage system; and an ID management unit which manages said first IDs and said second IDs in a corresponding manner for each of said computers; wherein a first communication protocol for communication with said computers is different from a second communication protocol for communication with said storage system, wherein the first IDs are based on requirements of the first communication protocol, and the second IDs are based on requirements of the second communication protocol, such that the first IDs and second IDs differ from each other.
    Type: Application
    Filed: March 2, 2009
    Publication date: July 2, 2009
    Inventors: Kenichi Shimooka, Masayuki Yamamoto, Hiroshi Furukawa
  • Patent number: 7554936
    Abstract: A radio network can select a route of minimum path loss among entire relay routes and can set the relay route so as to satisfactorily resist interference. The radio network has a core node connected to a wired network, relay nodes each relaying at least one of a down-link data packet transmitted from the core node and an up-link data packet directed toward the core node, and a terminal station capable of transmission and reception of data packets with both the core node and the relay node. The relay node has total path loss optimized to be minimum between relay nodes included in a relay route of the data packet or between the relay node and the core node or both.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: June 30, 2009
    Assignee: NEC Corporation
    Inventors: Hiroshi Furukawa, Morihisa Momona, Koichi Ebata
  • Patent number: 7552034
    Abstract: When locating base stations which are wirelessly coupled with each other and establish one or more inter-cell wireless relay routes in a mobile communications system, the heights of directional antennas to be installed at the base stations are determined so as to be different, which base stations are adjacent with each other in a given inter-cell wireless relay route.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: June 23, 2009
    Assignee: NEC Corporation
    Inventors: Koichi Ebata, Hiroshi Furukawa
  • Patent number: 7512873
    Abstract: A parallel processing apparatus dynamically switching over a circuit configuration includes a plurality of computing elements, a network establishing connections between the plural computing elements, a plurality of selectors provided corresponding to the plurality of computing elements within the network and controlling outputs from the computing elements, first local memories stored with data used for the operations by the computing elements and connected to the respective computing elements, and second local memories stored with data used for controlling the connections by the selectors and connected to the respective selectors.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: March 31, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Hiroshi Furukawa
  • Publication number: 20080288825
    Abstract: In a storage subsystem which is connected to an IP network, by excluding an improper packet, security is heightened, and a performance of communication to a logical unit of storage subsystem is maintained and secured. In the storage subsystem, a function which carries out filtering of a packet other than an iSCSI packet is provided. With respect to only the packet passed through the function, its accessibility to the logical unit is filtered. Also, traffic of all received packets, and a traffic lob of a packet judged to be discarded by the above filtering is recorded. By using this information, controlling such as a cut-off process of improper communication, QoS securement for normal communication and so on, are carried out.
    Type: Application
    Filed: July 28, 2008
    Publication date: November 20, 2008
    Inventors: Hiroshi FURUKAWA, Etsutaro Akagawa