Patents by Inventor Hiroshi Inagawa

Hiroshi Inagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230387219
    Abstract: A method of manufacturing a semiconductor device includes: forming a silicon oxide film covering each of a first main surface and a second main surface of a semiconductor substrate; forming a redistribution wiring on the first main surface side of the semiconductor substrate; and grinding the second main surface of the semiconductor substrate. This grinding step is performed in a state in which a thickness of the silicon oxide film positioned on the second main surface is equal to or larger than 10 nm and equal to or smaller than 30 nm.
    Type: Application
    Filed: March 16, 2023
    Publication date: November 30, 2023
    Inventors: Futoshi KOMATSU, Tomoo NAKAYAMA, Katsuhiro UCHIMURA, Hiroshi INAGAWA
  • Patent number: 11652072
    Abstract: To improve reliability of a semiconductor device. There are provided the semiconductor device and a method of manufacturing the same, the semiconductor including a pad electrode that is formed over a semiconductor substrate and includes a first conductive film and a second conductive film formed over the first conductive film, and a plating film that is formed over the second conductive film and used to be coupled to an external connection terminal (TR). The first conductive film and the second conductive film contains mainly aluminum. The crystal surface on the surface of the first conductive film is different from the crystal surface on the surface of the second conductive film.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: May 16, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Tonegawa, Hiroshi Inagawa
  • Publication number: 20210225789
    Abstract: To improve reliability of a semiconductor device. There are provided the semiconductor device and a method of manufacturing the same, the semiconductor including a pad electrode that is formed over a semiconductor substrate and includes a first conductive film and a second conductive film formed over the first conductive film, and a plating film that is formed over the second conductive film and used to be coupled to an external connection terminal (TR). The first conductive film and the second conductive film contains mainly aluminum. The crystal surface on the surface of the first conductive film is different from the crystal surface on the surface of the second conductive film.
    Type: Application
    Filed: April 8, 2021
    Publication date: July 22, 2021
    Inventors: Takashi TONEGAWA, Hiroshi INAGAWA
  • Publication number: 20190067225
    Abstract: To improve reliability of a semiconductor device. There are provided the semiconductor device and a method of manufacturing the same, the semiconductor including a pad electrode that is formed over a semiconductor substrate and includes a first conductive film and a second conductive film formed over the first conductive film, and a plating film that is formed over the second conductive film and used to be coupled to an external connection terminal (TR). The first conductive film and the second conductive film contains mainly aluminum. The crystal surface on the surface of the first conductive film is different from the crystal surface on the surface of the second conductive film.
    Type: Application
    Filed: July 6, 2018
    Publication date: February 28, 2019
    Inventors: Takashi Tonegawa, Hiroshi Inagawa
  • Patent number: 9793342
    Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: October 17, 2017
    Assignees: Renesas Electronics Corporation, Renesas Semiconductor Package & Test Solutions Co., Ltd
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
  • Patent number: 9614055
    Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: April 4, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
  • Publication number: 20160111490
    Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.
    Type: Application
    Filed: December 21, 2015
    Publication date: April 21, 2016
    Inventors: Hiroshi INAGAWA, Nobuo MACHIDA, Kentaro OISHI
  • Patent number: 9246000
    Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: January 26, 2016
    Assignees: Renesas Electronics Corporation, Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
  • Publication number: 20160005819
    Abstract: Contact resistance between a SiC substrate and an electrode is decreased. When a silicide layer is analyzed by Auger Electron Spectroscopy (AES) sputter in a direction from a titanium layer side to a SiC substrate side, sputtering time corresponding to a depth profile of the silicide layer is defined as ts. In this case, a depth profile of the silicide layer from the titanium layer side in a range of sputtering time from 0.4ts to ts contains a region where titanium atoms determined by the AES sputter accounts for 5 at % or more of all atoms determined by the AES sputter.
    Type: Application
    Filed: June 13, 2015
    Publication date: January 7, 2016
    Inventors: Takahiro Kainuma, Takashi Igarashi, Hiroshi Inagawa, Takeshi Arai, Yuji Fujii, Takahiro Okamura, Hisashi Toyoda
  • Publication number: 20150179763
    Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.
    Type: Application
    Filed: February 18, 2015
    Publication date: June 25, 2015
    Inventors: Hiroshi INAGAWA, Nobuo MACHIDA, Kentaro OOISHI
  • Patent number: 8987810
    Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: March 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
  • Publication number: 20140145259
    Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.
    Type: Application
    Filed: January 31, 2014
    Publication date: May 29, 2014
    Applicants: HITACHI ULSI SYSTEMS CO., LTD., RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi INAGAWA, Nobuo MACHIDA, Kentaro OOISHI
  • Publication number: 20140110780
    Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.
    Type: Application
    Filed: December 30, 2013
    Publication date: April 24, 2014
    Applicants: Renesas Eastern Japan Semiconductor, Inc., Renesas Electronics Corporation
    Inventors: Hiroshi INAGAWA, Nobuo MACHIDA, Kentaro OISHI
  • Patent number: 8704291
    Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: April 22, 2014
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
  • Patent number: 8642401
    Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: February 4, 2014
    Assignees: Renesas Electronics Corporation, Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
  • Patent number: 8378413
    Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: February 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
  • Patent number: 8377775
    Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: February 19, 2013
    Assignees: Renesas Electronics Corporation, Hitachi Tobu Semiconductor, Ltd.
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
  • Publication number: 20120289013
    Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.
    Type: Application
    Filed: July 26, 2012
    Publication date: November 15, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi INAGAWA, Nobuo MACHIDA, Kentaro OOISHI
  • Patent number: 8299495
    Abstract: In a reverse conducting IGBT, diode cathode regions are formed dispersedly on the back side of a device chip. When the distribution density of the diode cathode region becomes low, VF of a fly-back diode, that is, a forward voltage drop becomes large. On the other hand, when the distribution density of the diode cathode region becomes high, it becomes hard for a PN junction at a collector part to turn ON and a snap back occurs. In contrast to this, there is a method of providing about one to several diode cathode absent regions having a macro area, however, the arrangement of the regions itself directly affects the device characteristics, and therefore, it is difficult to control the device characteristics and variations thereof.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: October 30, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshi Inagawa
  • Patent number: 8278708
    Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: October 2, 2012
    Assignees: Renesas Electronics Corporation, Hitachi Tobu Semiconductor Ltd.
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi