Patents by Inventor Hiroshi Inagawa
Hiroshi Inagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120142156Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: ApplicationFiled: February 15, 2012Publication date: June 7, 2012Applicants: Hitachi Tobu Semiconductor, Ltd., Renesas Electronics CorporationInventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Publication number: 20120139040Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: ApplicationFiled: February 15, 2012Publication date: June 7, 2012Applicants: Hitachi Tobu Semiconductor, Ltd., Renesas Electronics CorporationInventors: HIROSHI INAGAWA, Nobuo Machida, Kentaro Oishi
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Patent number: 8168498Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: December 7, 2010Date of Patent: May 1, 2012Assignees: Renesas Electronics Corporation, Hitachi Tobu Semiconductor, Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Patent number: 8148224Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: September 23, 2011Date of Patent: April 3, 2012Assignees: Renesas Electronics Corporation, Hitachi Tobu Semiconductor, Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Publication number: 20120015492Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: ApplicationFiled: September 23, 2011Publication date: January 19, 2012Applicants: Hitachi Tobu Semiconductor, Ltd., Renesas Electronics CorporationInventors: HIROSHI INAGAWA, Nobuo Machida, Kentaro Oishi
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Publication number: 20110180902Abstract: In a reverse conducting IGBT, diode cathode regions are formed dispersedly on the back side of a device chip. When the distribution density of the diode cathode region becomes low, VF of a fly-back diode, that is, a forward voltage drop becomes large. On the other hand, when the distribution density of the diode cathode region becomes high, it becomes hard for a PN junction at a collector part to turn ON and a snap back occurs. In contrast to this, there is a method of providing about one to several diode cathode absent regions having a macro area, however, the arrangement of the regions itself directly affects the device characteristics, and therefore, it is difficult to control the device characteristics and variations thereof.Type: ApplicationFiled: January 26, 2011Publication date: July 28, 2011Inventor: HIROSHI INAGAWA
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Publication number: 20110140198Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.Type: ApplicationFiled: February 22, 2011Publication date: June 16, 2011Applicants: RENESAS ELECTRONICS CORPORATION, HITACHI ULSI SYSTEMS, CO., LTD.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Publication number: 20110076818Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: ApplicationFiled: December 7, 2010Publication date: March 31, 2011Applicants: Renesas Electronics Corporation, Hitachi Tobu Semiconductor, Ltd.Inventors: HIROSHI INAGAWA, Nobuo Machida, Kentaro Oishi
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Patent number: 7910985Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.Type: GrantFiled: April 14, 2010Date of Patent: March 22, 2011Assignee: Renesas Electronics CorporationInventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Patent number: 7910990Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: August 25, 2010Date of Patent: March 22, 2011Assignees: Renesas Electronics Corporation, Hitachi Tobu Semiconductor, Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Publication number: 20100320533Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: ApplicationFiled: August 25, 2010Publication date: December 23, 2010Applicants: Renesas Electronics Corporation, Hitachi Tobu Semiconductor, Ltd.Inventors: HIROSHI INAGAWA, Nobuo Machida, Kentaro Oishi
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Patent number: 7843001Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: August 11, 2009Date of Patent: November 30, 2010Assignees: Renesas Electronics Corporation, Hitachi Tobu Semiconductor Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Publication number: 20100193863Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.Type: ApplicationFiled: April 14, 2010Publication date: August 5, 2010Applicants: RENESAS TECHNOLOGY CORP., HITACHI ULSI SYSTEMS, CO., LTD.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Patent number: 7723753Abstract: In a GaAs substrate as a semi-insulating substrate, a heterojunction bipolar transistor (HBT) is formed in an element formation region, while an isolation region is formed in an insulating region. The isolation region formed in the insulating region is formed by introducing helium into the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT. In an outer peripheral region, a conductive layer is formed to be exposed from protective films and coupled to a back surface electrode. Because a GND potential is supplied to the back surface electrode, the conductive layer is fixed to the GND potential. The conductive layer is formed of the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT.Type: GrantFiled: December 21, 2007Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Kenji Sasaki, Ikuro Akazawa, Yoshinori Imamura, Atsushi Kurokawa, Tatsuhiko Ikeda, Hiroshi Inagawa, Yasunari Umemoto, Isao Obu
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Publication number: 20090294845Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: ApplicationFiled: August 11, 2009Publication date: December 3, 2009Applicants: Renesas Technology Corp., Hitachi Tobu Semiconductor, Ltd.Inventors: HIROSHI INAGAWA, Nobuo Machida, Kentaro Oishi
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Patent number: 7585732Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: February 26, 2008Date of Patent: September 8, 2009Assignees: Renesas Technology Corp., Hitachi Tobu Semiconductor, Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Patent number: 7433646Abstract: Disclosed is a learning support method with a server computer. Presupposed keywords corresponding to subjects that should have been acquired by a learner before attending a learning course and learning keywords corresponding to subjects that will be acquired by attending the learning course are defined for the learning course. The learning material is developed in module basis. Presupposed keywords corresponding to subjects that should have been acquired by a learner before learning the module and learning keywords corresponding to subjects that will be acquired by learning the module are defined for each module. The server computer selects a module whose learning keywords match the learning keywords of the learning course attended by a leaner and whose presupposed keywords match the keywords corresponding to subjects that have been learned by the learner, supplying the module to the learner.Type: GrantFiled: January 17, 2003Date of Patent: October 7, 2008Assignee: Fujitsu LimitedInventors: Akio Fujino, Hiroshi Inagawa, Tomohisa Misawa
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Publication number: 20080233696Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.Type: ApplicationFiled: February 22, 2008Publication date: September 25, 2008Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Publication number: 20080224174Abstract: A technology which allows an improvement in the moisture resistance of a semiconductor device is provided. In a GaAs substrate as a semi-insulating substrate, a HBT is formed in an element formation region, while an isolation region is formed in an insulating region. The isolation region formed in the insulating region is formed by introducing helium into the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT. In an outer peripheral region, a conductive layer is formed to be exposed from protective films and coupled to a back surface electrode. Because a GND potential is supplied to the back surface electrode, the conductive layer is fixed to the GND potential. The conductive layer is formed of the same semiconductor layers as the sub-collector semiconductor layer and collector semiconductor layer of the HBT.Type: ApplicationFiled: December 21, 2007Publication date: September 18, 2008Inventors: Kenji SASAKI, Ikuro Akazawa, Yoshinori Imamura, Atsushi Kurokawa, Tatsuhiko Ikeda, Hiroshi Inagawa, Yasunari Umemoto, Isao Obu
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Publication number: 20080153235Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: ApplicationFiled: February 26, 2008Publication date: June 26, 2008Applicants: Renesas Technology Corp., Hitachi Tobu Semiconductor, Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi