Patents by Inventor Hiroshi Inagawa
Hiroshi Inagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7378690Abstract: Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.Type: GrantFiled: March 26, 2007Date of Patent: May 27, 2008Assignee: Renesas Technology Corp.Inventors: Atsushi Kurokawa, Hiroshi Inagawa, Toshiaki Kitahara, Yoshinori Imamura
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Patent number: 7361557Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: January 16, 2007Date of Patent: April 22, 2008Assignees: Renesas Technology Corp., Hitachi Tobu Semiconductor Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Patent number: 7358141Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.Type: GrantFiled: July 11, 2006Date of Patent: April 15, 2008Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Publication number: 20070176207Abstract: Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.Type: ApplicationFiled: March 26, 2007Publication date: August 2, 2007Inventors: Atsushi Kurokawa, Hiroshi Inagawa, Toshiaki Kitahara, Yoshinori Imamura
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Publication number: 20070117329Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: ApplicationFiled: January 16, 2007Publication date: May 24, 2007Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Patent number: 7214558Abstract: Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.Type: GrantFiled: October 25, 2005Date of Patent: May 8, 2007Assignee: Renesas Technology Corp.Inventors: Atsushi Kurokawa, Hiroshi Inagawa, Toshiaki Kitahara, Yoshinori Imamura
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Publication number: 20070059853Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN).Type: ApplicationFiled: October 31, 2006Publication date: March 15, 2007Inventors: Atsushi KUROKAWA, Toshiaki Kitahara, Hiroshi Inagawa, Yoshinori Imamura
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Patent number: 7189621Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed higher than the main surface of the semiconductor substrate and the trench gate conductive layer and gate insulating film are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench.Type: GrantFiled: November 12, 2004Date of Patent: March 13, 2007Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Patent number: 7172941Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: GrantFiled: November 10, 2004Date of Patent: February 6, 2007Assignees: Renesas Technology Corp., Hitachi Tobu Semiconductor Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Publication number: 20060252192Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.Type: ApplicationFiled: July 11, 2006Publication date: November 9, 2006Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Patent number: 7132320Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN).Type: GrantFiled: November 4, 2005Date of Patent: November 7, 2006Assignee: Renesas Technology Corp.Inventors: Atsushi Kurokawa, Toshiaki Kitahara, Hiroshi Inagawa, Yoshinori Imamura
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Patent number: 7098506Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.Type: GrantFiled: January 31, 2005Date of Patent: August 29, 2006Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Patent number: 7029938Abstract: Upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa is formed, followed by successive formation of gold germanium, nickel and Au in this order over the entire surface of a substrate, so that the resulting stacked film will not become an isolated pattern. Thus, the stacked film over the base mesa is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa. Generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material which hardly reacts with an n-type GaAs layer or n-type InGaAs layer.Type: GrantFiled: March 26, 2004Date of Patent: April 18, 2006Assignee: Renesas Technology Corp.Inventors: Atsushi Kurokawa, Hiroshi Inagawa, Toshiaki Kitahara, Yoshinori Imamura
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Publication number: 20060057789Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN).Type: ApplicationFiled: November 4, 2005Publication date: March 16, 2006Inventors: Atsushi Kurokawa, Toshiaki Kitahara, Hiroshi Inagawa, Yoshinori Imamura
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Publication number: 20060032762Abstract: Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.Type: ApplicationFiled: October 25, 2005Publication date: February 16, 2006Inventors: Atsushi Kurokawa, Hiroshi Inagawa, Toshiaki Kitahara, Yoshinori Imamura
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Patent number: 6989301Abstract: The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN).Type: GrantFiled: September 30, 2003Date of Patent: January 24, 2006Assignee: Renesas Technology Corp.Inventors: Atsushi Kurokawa, Toshiaki Kitahara, Hiroshi Inagawa, Yoshinori Imamura
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Publication number: 20050182640Abstract: A safety-related information delivering apparatus comprises a unit determining whether a person who desires the delivery of safety-related information desires schedule-delivery of information according to his or her schedule or the zone-delivery of information according to his or her current location, and a unit delivering the safety-related information in correspondence with a determination result.Type: ApplicationFiled: July 22, 2004Publication date: August 18, 2005Applicant: FUJITSU LIMITEDInventors: Kosei Takano, Takashi Tsuchida, Akio Fujino, Hiroshi Inagawa, Tomohisa Misawa, Daiji Yamano
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Publication number: 20050127437Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.Type: ApplicationFiled: January 31, 2005Publication date: June 16, 2005Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi
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Publication number: 20050082609Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.Type: ApplicationFiled: November 10, 2004Publication date: April 21, 2005Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
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Publication number: 20050082608Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed higher than the main surface of the semiconductor substrate and the trench gate conductive layer and gate insulating film are formed in the trench and over the main surface of the semiconductor substrate at the periphery of the trench.Type: ApplicationFiled: November 12, 2004Publication date: April 21, 2005Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Ooishi