Patents by Inventor Hiroshi Itokawa
Hiroshi Itokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230073505Abstract: A semiconductor storage device includes: a plurality of conductive layers arranged in a first direction; a semiconductor layer extending in the first direction and facing the plurality of conductive layers; a charge storage layer provided between the plurality of conductive layers and the semiconductor layer; a first structure disposed apart from the semiconductor layer in a second direction intersecting the first direction, extending in a third direction intersecting the first direction and the second direction, and facing the plurality of conductive layers; and a plurality of first nitride films containing nitrogen (N), and covering surfaces of the plurality of conductive layers facing the first structure.Type: ApplicationFiled: March 1, 2022Publication date: March 9, 2023Applicant: Kioxia CorporationInventors: Takashi FUKUSHIMA, Yuji SAKAI, Hiroshi ITOKAWA, Tatsunori ISOGAI, Ryosuke SAWABE
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Patent number: 11581329Abstract: A semiconductor memory device comprises a semiconductor, a first insulator, a second insulator, a first conductor, a third insulator, a fourth insulator, and a fifth insulator. The first insulator is on the semiconductor. The second insulator is on the first insulator. The third insulator is on the first conductor. The fourth insulator is between the second insulator and the first conductor. The fifth insulator is provided between the second insulator and the third insulator. The fifth insulator is having an oxygen concentration different from an oxygen concentration of the fourth insulator.Type: GrantFiled: August 21, 2020Date of Patent: February 14, 2023Assignee: Kioxia CorporationInventors: Ryosuke Sawabe, Yasuhiro Uchiyama, Hiroshi Itokawa
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Patent number: 11257832Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, a second insulating film provided between the second electrode and the first insulating film and on two first-direction sides of the second electrode, a third insulating film provided between the second electrode and the semiconductor pillar, and a conductive film provided inside a region interposed between the first insulating film and the second insulating film.Type: GrantFiled: August 23, 2017Date of Patent: February 22, 2022Assignee: Kioxia CorporationInventors: Tatsuya Kato, Fumitaka Arai, Katsuyuki Sekine, Toshiyuki Iwamoto, Yuta Watanabe, Wataru Sakamoto, Hiroshi Itokawa
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Patent number: 11183507Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.Type: GrantFiled: August 22, 2017Date of Patent: November 23, 2021Assignee: Toshiba Memory CorporationInventors: Katsuyuki Sekine, Tatsuya Kato, Fumitaka Arai, Toshiyuki Iwamoto, Yuta Watanabe, Wataru Sakamoto, Hiroshi Itokawa, Akio Kaneko
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Publication number: 20210057446Abstract: A semiconductor memory device comprises a semiconductor, a first insulator, a second insulator, a first conductor, a third insulator, a fourth insulator, and a fifth insulator. The first insulator is on the semiconductor. The second insulator is on the first insulator. The third insulator is on the first conductor. The fourth insulator is between the second insulator and the first conductor. The fifth insulator is provided between the second insulator and the third insulator. The fifth insulator is having an oxygen concentration different from an oxygen concentration of the fourth insulator.Type: ApplicationFiled: August 21, 2020Publication date: February 25, 2021Applicant: Kioxia CorporationInventors: Ryosuke SAWABE, Yasuhiro UCHIYAMA, Hiroshi ITOKAWA
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Patent number: 10636807Abstract: A semiconductor memory device includes a stacked body, a semiconductor portion, a first insulating film, a charge storage layer, and a second insulating film. The stacked body has a plurality of electrode layers stacked in a spaced apart manner from each other. The semiconductor portion is provided in the stacked body and extends in a first direction where the plurality of electrode layers are stacked. The first insulating film is provided between the plurality of electrode layers and the semiconductor portion. The charge storage layer is provided between the plurality of electrode layers and the first insulating film and contains a compound including at least one of hafnium oxide or zirconium oxide and a first material having a valence lower than that of the at least one of the hafnium oxide or the zirconium oxide.Type: GrantFiled: March 2, 2018Date of Patent: April 28, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroshi Itokawa, Takashi Furuhashi
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Patent number: 10566280Abstract: In one embodiment, a semiconductor device includes a first insulator. The device further includes a metal layer that includes a first metal layer provided on a surface of the first insulator, and a second metal layer provided on a surface of the first metal layer and containing a first metallic element and oxygen or containing aluminum and nitrogen, or includes a third metal layer provided on the surface of the first insulator and containing a second metallic element, aluminum and nitrogen. The device further includes an interconnect material layer provided on a surface of the metal layer.Type: GrantFiled: August 14, 2018Date of Patent: February 18, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Satoshi Wakatsuki, Masayuki Kitamura, Takeshi Ishizaki, Hiroshi Itokawa, Daisuke Ikeno, Kei Watanabe, Atsuko Sakata
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Publication number: 20190279932Abstract: In one embodiment, a semiconductor device includes a first insulator. The device further includes a metal layer that includes a first metal layer provided on a surface of the first insulator, and a second metal layer provided on a surface of the first metal layer and containing a first metallic element and oxygen or containing aluminum and nitrogen, or includes a third metal layer provided on the surface of the first insulator and containing a second metallic element, aluminum and nitrogen. The device further includes an interconnect material layer provided on a surface of the metal layer.Type: ApplicationFiled: August 14, 2018Publication date: September 12, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Satoshi WAKATSUKI, Masayuki KITAMURA, Takeshi ISHIZAKI, Hiroshi ITOKAWA, Daisuke IKENO, Kei WATANABE, Atsuko SAKATA
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Publication number: 20190088675Abstract: A semiconductor memory device includes a stacked body, a semiconductor portion, a first insulating film, a charge storage layer, and a second insulating film. The stacked body has a plurality of electrode layers stacked in a spaced apart manner from each other. The semiconductor portion is provided in the stacked body and extends in a first direction where the plurality of electrode layers are stacked. The first insulating film is provided between the plurality of electrode layers and the semiconductor portion. The charge storage layer is provided between the plurality of electrode layers and the first insulating film and contains a compound including at least one of hafnium oxide or zirconium oxide and a first material having a valence lower than that of the at least one of the hafnium oxide or the zirconium oxide.Type: ApplicationFiled: March 2, 2018Publication date: March 21, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hiroshi ITOKAWA, Takashi FURUHASHI
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Publication number: 20190018440Abstract: A rotational operation device includes a light source configured to output illumination light, a display portion including plural display targets formed in a circumferential direction, a transmission region that transmits the illumination light, and a light-blocking region that blocks the illumination light, and an operation part configured to rotate together with the display portion in accordance with a performed rotation operation. The operation part is opaque and allows visual recognition of the plurality of display targets by the illumination light output from the light source and transmitted through the transmission region of the display portion.Type: ApplicationFiled: February 1, 2017Publication date: January 17, 2019Inventors: Shinya ISHIMARU, Hiroshi ITOKAWA
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Patent number: 9972635Abstract: A semiconductor memory device according to one embodiment, includes an interconnect extending in a first direction, a semiconductor member extending in a second direction crossing the first direction, an electrode provided between the interconnect and the semiconductor member, a first insulating film provided between the interconnect and the electrode, a second insulating film provided between the first insulating film and the electrode, a third insulating film provided between the electrode and the semiconductor member, and a metal-containing layer provided between the first insulating film and the second insulating film or inside the first insulating film, and having a metal surface concentration of 1×1014 cm?2 or more and 5×1015 cm?2 or less.Type: GrantFiled: September 16, 2016Date of Patent: May 15, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Hiroshi Itokawa
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Publication number: 20170373082Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.Type: ApplicationFiled: August 22, 2017Publication date: December 28, 2017Applicant: Toshiba Memory CorporationInventors: Katsuyuki SEKINE, Tatsuya KATO, Fumitaka ARAI, Toshiyuki IWAMOTO, Yuta WATANABE, Wataru SAKAMOTO, Hiroshi ITOKAWA, Akio KANEKO
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Publication number: 20170352671Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, a second insulating film provided between the second electrode and the first insulating film and on two first-direction sides of the second electrode, a third insulating film provided between the second electrode and the semiconductor pillar, and a conductive film provided inside a region interposed between the first insulating film and the second insulating film.Type: ApplicationFiled: August 23, 2017Publication date: December 7, 2017Applicant: Toshiba Memory CorporationInventors: Tatsuya Kato, Fumitaka Arai, Katsuyuki Sekine, Toshiyuki Iwamoto, Yuta Watanabe, Wataru Sakamoto, Hiroshi Itokawa
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Publication number: 20170250189Abstract: A semiconductor memory device according to one embodiment, includes an interconnect extending in a first direction, a semiconductor member extending in a second direction crossing the first direction, an electrode provided between the interconnect and the semiconductor member, a first insulating film provided between the interconnect and the electrode, a second insulating film provided between the first insulating film and the electrode, a third insulating film provided between the electrode and the semiconductor member, and a metal-containing layer provided between the first insulating film and the second insulating film or inside the first insulating film, and having a metal surface concentration of 1×1014 cm?2 or more and 5×1015 cm?2 or less.Type: ApplicationFiled: September 16, 2016Publication date: August 31, 2017Applicant: Kabushiki Kaisha ToshibaInventor: Hiroshi ITOKAWA
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Patent number: 9613974Abstract: According to one embodiment, the contact electrode extends in the inter-layer insulating layer toward the second semiconductor region. The metal silicide film is in contact with the second semiconductor region and the contact electrode. The metal silicide film includes a first part and a second part. The first part is provided between a bottom of the contact electrode and the second semiconductor region. The second part is provided on a surface of the second semiconductor region between the first part and the gate electrode. A bottom of the second part is located at a position shallower than a bottom the first part.Type: GrantFiled: August 10, 2015Date of Patent: April 4, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Hiroki Okamoto, Hiroshi Itokawa, Masayuki Kitamura, Atsushi Yagishita
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Patent number: 9484262Abstract: Effective transfer of stress to a channel of a fin field effect transistor is provided by forming stress-generating active semiconductor regions that function as a source region and a drain region on a top surface of a single crystalline semiconductor layer. A dielectric material layer is formed on a top surface of the semiconductor layer between semiconductor fins. A gate structure is formed across the semiconductor fins, and the dielectric material layer is patterned employing the gate structure as an etch mask. A gate spacer is formed around the gate stack, and physically exposed portions of the semiconductor fins are removed by an etch. Stress-generating active semiconductor regions are formed by selective epitaxy from physically exposed top surfaces of the semiconductor layer, and apply stress to remaining portions of the semiconductor fins that include channels.Type: GrantFiled: October 13, 2015Date of Patent: November 1, 2016Assignee: International Business Machines CorporationInventors: Veeraraghavan S. Basker, Akira Hokazono, Hiroshi Itokawa, Tenko Yamashita, Chun-chen Yeh
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Publication number: 20160268285Abstract: According to one embodiment, the contact electrode extends in the inter-layer insulating layer toward the second semiconductor region. The metal silicide film is in contact with the second semiconductor region and the contact electrode. The metal silicide film includes a first part and a second part. The first part is provided between a bottom of the contact electrode and the second semiconductor region. The second part is provided on a surface of the second semiconductor region between the first part and the gate electrode. A bottom of the second part is located at a position shallower than a bottom the first part.Type: ApplicationFiled: August 10, 2015Publication date: September 15, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Hiroki OKAMOTO, Hiroshi Itokawa, Masayuki Kitamura, Atsushi Yagishita
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Publication number: 20160268388Abstract: A non-volatile memory device includes a semiconductor body extending in a first direction, an electrode extending in a second direction crossing the first direction, a first floating gate provided between the semiconductor body and the electrode, and a second floating gate provided between the first floating gate and the electrode. The first floating gate is provided via an insulating film on the semiconductor body and has a side surface in the second direction. The second floating gate has a side surface in the second direction. The device further includes a silicon nitride film in contact with the side surface of the second floating gate and a first insulating film that covers the silicon nitride film and is in contact with the side surface of the first floating gate.Type: ApplicationFiled: August 28, 2015Publication date: September 15, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi ITOKAWA, Kenichiro TORATANI
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Patent number: 9263319Abstract: According to one embodiment, a semiconductor memory device includes a plurality of stacked bodies and a spacer film provided on a side surface of the stacked bodies. Each of the plurality of stacked bodies includes a silicon electrode and a metal electrode stacked on the metal electrode. The plurality of stacked bodies are separated from each other by an air gap. The spacer film includes silicon oxide. A portion of the spacer film disposed on a side surface of the metal electrode is thicker than a portion of the spacer film disposed on a side surface of the silicon electrode.Type: GrantFiled: June 9, 2014Date of Patent: February 16, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Ryota Fujitsuka, Fumiki Aiso, Motoki Fujii, Hiroshi Itokawa
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Publication number: 20160035626Abstract: Effective transfer of stress to a channel of a fin field effect transistor is provided by forming stress-generating active semiconductor regions that function as a source region and a drain region on a top surface of a single crystalline semiconductor layer. A dielectric material layer is formed on a top surface of the semiconductor layer between semiconductor fins. A gate structure is formed across the semiconductor fins, and the dielectric material layer is patterned employing the gate structure as an etch mask. A gate spacer is formed around the gate stack, and physically exposed portions of the semiconductor fins are removed by an etch. Stress-generating active semiconductor regions are formed by selective epitaxy from physically exposed top surfaces of the semiconductor layer, and apply stress to remaining portions of the semiconductor fins that include channels.Type: ApplicationFiled: October 13, 2015Publication date: February 4, 2016Inventors: Veeraraghavan S. Basker, Akira Hokazono, Hiroshi Itokawa, Tenko Yamashita, Chun-chen Yeh