Patents by Inventor Hiroshi Itokawa

Hiroshi Itokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190279932
    Abstract: In one embodiment, a semiconductor device includes a first insulator. The device further includes a metal layer that includes a first metal layer provided on a surface of the first insulator, and a second metal layer provided on a surface of the first metal layer and containing a first metallic element and oxygen or containing aluminum and nitrogen, or includes a third metal layer provided on the surface of the first insulator and containing a second metallic element, aluminum and nitrogen. The device further includes an interconnect material layer provided on a surface of the metal layer.
    Type: Application
    Filed: August 14, 2018
    Publication date: September 12, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi WAKATSUKI, Masayuki KITAMURA, Takeshi ISHIZAKI, Hiroshi ITOKAWA, Daisuke IKENO, Kei WATANABE, Atsuko SAKATA
  • Publication number: 20190088675
    Abstract: A semiconductor memory device includes a stacked body, a semiconductor portion, a first insulating film, a charge storage layer, and a second insulating film. The stacked body has a plurality of electrode layers stacked in a spaced apart manner from each other. The semiconductor portion is provided in the stacked body and extends in a first direction where the plurality of electrode layers are stacked. The first insulating film is provided between the plurality of electrode layers and the semiconductor portion. The charge storage layer is provided between the plurality of electrode layers and the first insulating film and contains a compound including at least one of hafnium oxide or zirconium oxide and a first material having a valence lower than that of the at least one of the hafnium oxide or the zirconium oxide.
    Type: Application
    Filed: March 2, 2018
    Publication date: March 21, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroshi ITOKAWA, Takashi FURUHASHI
  • Publication number: 20190018440
    Abstract: A rotational operation device includes a light source configured to output illumination light, a display portion including plural display targets formed in a circumferential direction, a transmission region that transmits the illumination light, and a light-blocking region that blocks the illumination light, and an operation part configured to rotate together with the display portion in accordance with a performed rotation operation. The operation part is opaque and allows visual recognition of the plurality of display targets by the illumination light output from the light source and transmitted through the transmission region of the display portion.
    Type: Application
    Filed: February 1, 2017
    Publication date: January 17, 2019
    Inventors: Shinya ISHIMARU, Hiroshi ITOKAWA
  • Patent number: 9972635
    Abstract: A semiconductor memory device according to one embodiment, includes an interconnect extending in a first direction, a semiconductor member extending in a second direction crossing the first direction, an electrode provided between the interconnect and the semiconductor member, a first insulating film provided between the interconnect and the electrode, a second insulating film provided between the first insulating film and the electrode, a third insulating film provided between the electrode and the semiconductor member, and a metal-containing layer provided between the first insulating film and the second insulating film or inside the first insulating film, and having a metal surface concentration of 1×1014 cm?2 or more and 5×1015 cm?2 or less.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: May 15, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroshi Itokawa
  • Publication number: 20170373082
    Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.
    Type: Application
    Filed: August 22, 2017
    Publication date: December 28, 2017
    Applicant: Toshiba Memory Corporation
    Inventors: Katsuyuki SEKINE, Tatsuya KATO, Fumitaka ARAI, Toshiyuki IWAMOTO, Yuta WATANABE, Wataru SAKAMOTO, Hiroshi ITOKAWA, Akio KANEKO
  • Publication number: 20170352671
    Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, a second insulating film provided between the second electrode and the first insulating film and on two first-direction sides of the second electrode, a third insulating film provided between the second electrode and the semiconductor pillar, and a conductive film provided inside a region interposed between the first insulating film and the second insulating film.
    Type: Application
    Filed: August 23, 2017
    Publication date: December 7, 2017
    Applicant: Toshiba Memory Corporation
    Inventors: Tatsuya Kato, Fumitaka Arai, Katsuyuki Sekine, Toshiyuki Iwamoto, Yuta Watanabe, Wataru Sakamoto, Hiroshi Itokawa
  • Publication number: 20170250189
    Abstract: A semiconductor memory device according to one embodiment, includes an interconnect extending in a first direction, a semiconductor member extending in a second direction crossing the first direction, an electrode provided between the interconnect and the semiconductor member, a first insulating film provided between the interconnect and the electrode, a second insulating film provided between the first insulating film and the electrode, a third insulating film provided between the electrode and the semiconductor member, and a metal-containing layer provided between the first insulating film and the second insulating film or inside the first insulating film, and having a metal surface concentration of 1×1014 cm?2 or more and 5×1015 cm?2 or less.
    Type: Application
    Filed: September 16, 2016
    Publication date: August 31, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi ITOKAWA
  • Patent number: 9613974
    Abstract: According to one embodiment, the contact electrode extends in the inter-layer insulating layer toward the second semiconductor region. The metal silicide film is in contact with the second semiconductor region and the contact electrode. The metal silicide film includes a first part and a second part. The first part is provided between a bottom of the contact electrode and the second semiconductor region. The second part is provided on a surface of the second semiconductor region between the first part and the gate electrode. A bottom of the second part is located at a position shallower than a bottom the first part.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: April 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroki Okamoto, Hiroshi Itokawa, Masayuki Kitamura, Atsushi Yagishita
  • Patent number: 9484262
    Abstract: Effective transfer of stress to a channel of a fin field effect transistor is provided by forming stress-generating active semiconductor regions that function as a source region and a drain region on a top surface of a single crystalline semiconductor layer. A dielectric material layer is formed on a top surface of the semiconductor layer between semiconductor fins. A gate structure is formed across the semiconductor fins, and the dielectric material layer is patterned employing the gate structure as an etch mask. A gate spacer is formed around the gate stack, and physically exposed portions of the semiconductor fins are removed by an etch. Stress-generating active semiconductor regions are formed by selective epitaxy from physically exposed top surfaces of the semiconductor layer, and apply stress to remaining portions of the semiconductor fins that include channels.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: November 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Akira Hokazono, Hiroshi Itokawa, Tenko Yamashita, Chun-chen Yeh
  • Publication number: 20160268285
    Abstract: According to one embodiment, the contact electrode extends in the inter-layer insulating layer toward the second semiconductor region. The metal silicide film is in contact with the second semiconductor region and the contact electrode. The metal silicide film includes a first part and a second part. The first part is provided between a bottom of the contact electrode and the second semiconductor region. The second part is provided on a surface of the second semiconductor region between the first part and the gate electrode. A bottom of the second part is located at a position shallower than a bottom the first part.
    Type: Application
    Filed: August 10, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroki OKAMOTO, Hiroshi Itokawa, Masayuki Kitamura, Atsushi Yagishita
  • Publication number: 20160268388
    Abstract: A non-volatile memory device includes a semiconductor body extending in a first direction, an electrode extending in a second direction crossing the first direction, a first floating gate provided between the semiconductor body and the electrode, and a second floating gate provided between the first floating gate and the electrode. The first floating gate is provided via an insulating film on the semiconductor body and has a side surface in the second direction. The second floating gate has a side surface in the second direction. The device further includes a silicon nitride film in contact with the side surface of the second floating gate and a first insulating film that covers the silicon nitride film and is in contact with the side surface of the first floating gate.
    Type: Application
    Filed: August 28, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi ITOKAWA, Kenichiro TORATANI
  • Patent number: 9263319
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of stacked bodies and a spacer film provided on a side surface of the stacked bodies. Each of the plurality of stacked bodies includes a silicon electrode and a metal electrode stacked on the metal electrode. The plurality of stacked bodies are separated from each other by an air gap. The spacer film includes silicon oxide. A portion of the spacer film disposed on a side surface of the metal electrode is thicker than a portion of the spacer film disposed on a side surface of the silicon electrode.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: February 16, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryota Fujitsuka, Fumiki Aiso, Motoki Fujii, Hiroshi Itokawa
  • Publication number: 20160035626
    Abstract: Effective transfer of stress to a channel of a fin field effect transistor is provided by forming stress-generating active semiconductor regions that function as a source region and a drain region on a top surface of a single crystalline semiconductor layer. A dielectric material layer is formed on a top surface of the semiconductor layer between semiconductor fins. A gate structure is formed across the semiconductor fins, and the dielectric material layer is patterned employing the gate structure as an etch mask. A gate spacer is formed around the gate stack, and physically exposed portions of the semiconductor fins are removed by an etch. Stress-generating active semiconductor regions are formed by selective epitaxy from physically exposed top surfaces of the semiconductor layer, and apply stress to remaining portions of the semiconductor fins that include channels.
    Type: Application
    Filed: October 13, 2015
    Publication date: February 4, 2016
    Inventors: Veeraraghavan S. Basker, Akira Hokazono, Hiroshi Itokawa, Tenko Yamashita, Chun-chen Yeh
  • Patent number: 9246005
    Abstract: Effective transfer of stress to a channel of a fin field effect transistor is provided by forming stress-generating active semiconductor regions that function as a source region and a drain region on a top surface of a single crystalline semiconductor layer. A dielectric material layer is formed on a top surface of the semiconductor layer between semiconductor fins. A gate structure is formed across the semiconductor fins, and the dielectric material layer is patterned employing the gate structure as an etch mask. A gate spacer is formed around the gate stack, and physically exposed portions of the semiconductor fins are removed by an etch. Stress-generating active semiconductor regions are formed by selective epitaxy from physically exposed top surfaces of the semiconductor layer, and apply stress to remaining portions of the semiconductor fins that include channels.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: January 26, 2016
    Assignees: International Business Machines Corporation, KABUSHIKI KAISHA TOSHIBA
    Inventors: Veeraraghavan S. Basker, Akira Hokazono, Hiroshi Itokawa, Tenko Yamashita, Chun-chen Yeh
  • Publication number: 20150255554
    Abstract: A semiconductor device includes a semiconductor substrate, a first insulation film disposed on the semiconductor substrate, a film including silicon disposed over the first insulation film, a second insulation film disposed on the film, and a plurality of metal dots disposed on the second insulation film, a semiconductor film selectively formed on the plurality of metal dots, and a high dielectric constant insulation film disposed on the semiconductor film and the second insulation film.
    Type: Application
    Filed: February 27, 2015
    Publication date: September 10, 2015
    Inventor: Hiroshi ITOKAWA
  • Publication number: 20150228789
    Abstract: Effective transfer of stress to a channel of a fin field effect transistor is provided by forming stress-generating active semiconductor regions that function as a source region and a drain region on a top surface of a single crystalline semiconductor layer. A dielectric material layer is formed on a top surface of the semiconductor layer between semiconductor fins. A gate structure is formed across the semiconductor fins, and the dielectric material layer is patterned employing the gate structure as an etch mask. A gate spacer is formed around the gate stack, and physically exposed portions of the semiconductor fins are removed by an etch. Stress-generating active semiconductor regions are formed by selective epitaxy from physically exposed top surfaces of the semiconductor layer, and apply stress to remaining portions of the semiconductor fins that include channels.
    Type: Application
    Filed: February 12, 2014
    Publication date: August 13, 2015
    Applicants: Kabushiki Kaisha Toshiba, International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Akira Hokazono, Hiroshi Itokawa, Tenko Yamashita, Chun-chen Yeh
  • Patent number: 9018061
    Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a silicon film including silicon provided on the first insulating film, a second insulating film provided on the silicon film, a hafnium alloy-containing film provided on the second insulating film, the hafnium alloy-containing film including oxygen and an alloy of hafnium and a metal other than hafnium, a third insulating film provided on the hafnium alloy-containing film, and an electrode provided on the third insulating film.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: April 28, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Itokawa
  • Publication number: 20150060986
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of stacked bodies and a spacer film provided on a side surface of the stacked bodies. Each of the plurality of stacked bodies includes a silicon electrode and a metal electrode stacked on the metal electrode. The plurality of stacked bodies are separated from each other by an air gap. The spacer film includes silicon oxide. A portion of the spacer film disposed on a side surface of the metal electrode is thicker than a portion of the spacer film disposed on a side surface of the silicon electrode.
    Type: Application
    Filed: June 9, 2014
    Publication date: March 5, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryota FUJITSUKA, Fumiki AISO, Motoki FUJII, Hiroshi ITOKAWA
  • Publication number: 20150060982
    Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a silicon film including silicon provided on the first insulating film, a second insulating film provided on the silicon film, a hafnium alloy-containing film provided on the second insulating film, the hafnium alloy-containing film including oxygen and an alloy of hafnium and a metal other than hafnium, a third insulating film provided on the hafnium alloy-containing film, and an electrode provided on the third insulating film.
    Type: Application
    Filed: January 13, 2014
    Publication date: March 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi ITOKAWA
  • Patent number: 8729607
    Abstract: Structures and methods are presented relating to formation of finFET semiconducting devices. A finFET device is presented comprising fin(s) formed on a substrate, wherein the fin(s) has a needle-shaped profile. The needle-shaped profile, in conjunction with at least a buffer layer or a doped layer, epitaxially formed on the fin(s), facilitates strain to be induced into the fin(s) by the buffer layer or the doped layer. The fin(s) can comprise silicon aligned on a first plane, while at least one of the buffer layer or the doped layer are grown on a second plane, the alignment of the first and second planes are disparate and are selected such that formation of the buffer layer or the doped layer generates a stress in the fin(s). The generated stress results in a strain being induced into the fin(s) channel region, which can improve electron and/or hole mobility in the channel.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Itokawa, Akira Hokazono