Patents by Inventor Hiroshi Itokawa
Hiroshi Itokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9246005Abstract: Effective transfer of stress to a channel of a fin field effect transistor is provided by forming stress-generating active semiconductor regions that function as a source region and a drain region on a top surface of a single crystalline semiconductor layer. A dielectric material layer is formed on a top surface of the semiconductor layer between semiconductor fins. A gate structure is formed across the semiconductor fins, and the dielectric material layer is patterned employing the gate structure as an etch mask. A gate spacer is formed around the gate stack, and physically exposed portions of the semiconductor fins are removed by an etch. Stress-generating active semiconductor regions are formed by selective epitaxy from physically exposed top surfaces of the semiconductor layer, and apply stress to remaining portions of the semiconductor fins that include channels.Type: GrantFiled: February 12, 2014Date of Patent: January 26, 2016Assignees: International Business Machines Corporation, KABUSHIKI KAISHA TOSHIBAInventors: Veeraraghavan S. Basker, Akira Hokazono, Hiroshi Itokawa, Tenko Yamashita, Chun-chen Yeh
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Publication number: 20150255554Abstract: A semiconductor device includes a semiconductor substrate, a first insulation film disposed on the semiconductor substrate, a film including silicon disposed over the first insulation film, a second insulation film disposed on the film, and a plurality of metal dots disposed on the second insulation film, a semiconductor film selectively formed on the plurality of metal dots, and a high dielectric constant insulation film disposed on the semiconductor film and the second insulation film.Type: ApplicationFiled: February 27, 2015Publication date: September 10, 2015Inventor: Hiroshi ITOKAWA
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Publication number: 20150228789Abstract: Effective transfer of stress to a channel of a fin field effect transistor is provided by forming stress-generating active semiconductor regions that function as a source region and a drain region on a top surface of a single crystalline semiconductor layer. A dielectric material layer is formed on a top surface of the semiconductor layer between semiconductor fins. A gate structure is formed across the semiconductor fins, and the dielectric material layer is patterned employing the gate structure as an etch mask. A gate spacer is formed around the gate stack, and physically exposed portions of the semiconductor fins are removed by an etch. Stress-generating active semiconductor regions are formed by selective epitaxy from physically exposed top surfaces of the semiconductor layer, and apply stress to remaining portions of the semiconductor fins that include channels.Type: ApplicationFiled: February 12, 2014Publication date: August 13, 2015Applicants: Kabushiki Kaisha Toshiba, International Business Machines CorporationInventors: Veeraraghavan S. Basker, Akira Hokazono, Hiroshi Itokawa, Tenko Yamashita, Chun-chen Yeh
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Patent number: 9018061Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a silicon film including silicon provided on the first insulating film, a second insulating film provided on the silicon film, a hafnium alloy-containing film provided on the second insulating film, the hafnium alloy-containing film including oxygen and an alloy of hafnium and a metal other than hafnium, a third insulating film provided on the hafnium alloy-containing film, and an electrode provided on the third insulating film.Type: GrantFiled: January 13, 2014Date of Patent: April 28, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Hiroshi Itokawa
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Publication number: 20150060986Abstract: According to one embodiment, a semiconductor memory device includes a plurality of stacked bodies and a spacer film provided on a side surface of the stacked bodies. Each of the plurality of stacked bodies includes a silicon electrode and a metal electrode stacked on the metal electrode. The plurality of stacked bodies are separated from each other by an air gap. The spacer film includes silicon oxide. A portion of the spacer film disposed on a side surface of the metal electrode is thicker than a portion of the spacer film disposed on a side surface of the silicon electrode.Type: ApplicationFiled: June 9, 2014Publication date: March 5, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Ryota FUJITSUKA, Fumiki AISO, Motoki FUJII, Hiroshi ITOKAWA
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Publication number: 20150060982Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a silicon film including silicon provided on the first insulating film, a second insulating film provided on the silicon film, a hafnium alloy-containing film provided on the second insulating film, the hafnium alloy-containing film including oxygen and an alloy of hafnium and a metal other than hafnium, a third insulating film provided on the hafnium alloy-containing film, and an electrode provided on the third insulating film.Type: ApplicationFiled: January 13, 2014Publication date: March 5, 2015Applicant: Kabushiki Kaisha ToshibaInventor: Hiroshi ITOKAWA
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Patent number: 8729607Abstract: Structures and methods are presented relating to formation of finFET semiconducting devices. A finFET device is presented comprising fin(s) formed on a substrate, wherein the fin(s) has a needle-shaped profile. The needle-shaped profile, in conjunction with at least a buffer layer or a doped layer, epitaxially formed on the fin(s), facilitates strain to be induced into the fin(s) by the buffer layer or the doped layer. The fin(s) can comprise silicon aligned on a first plane, while at least one of the buffer layer or the doped layer are grown on a second plane, the alignment of the first and second planes are disparate and are selected such that formation of the buffer layer or the doped layer generates a stress in the fin(s). The generated stress results in a strain being induced into the fin(s) channel region, which can improve electron and/or hole mobility in the channel.Type: GrantFiled: August 27, 2012Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Itokawa, Akira Hokazono
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Publication number: 20140054648Abstract: Structures and methods are presented relating to formation of finFET semiconducting devices. A finFET device is presented comprising fin(s) formed on a substrate, wherein the fin(s) has a needle-shaped profile. The needle-shaped profile, in conjunction with at least a buffer layer or a doped layer, epitaxially formed on the fin(s), facilitates strain to be induced into the fin(s) by the buffer layer or the doped layer. The fin(s) can comprise silicon aligned on a first plane, while at least one of the buffer layer or the doped layer are grown on a second plane, the alignment of the first and second planes are disparate and are selected such that formation of the buffer layer or the doped layer generates a stress in the fin(s). The generated stress results in a strain being induced into the fin(s) channel region, which can improve electron and/or hole mobility in the channel.Type: ApplicationFiled: August 27, 2012Publication date: February 27, 2014Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Inventors: Hiroshi Itokawa, Akira Hokazono
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Patent number: 8551871Abstract: A method of fabricating a semiconductor device according to one embodiment includes: exposing a surface of a semiconductor substrate to a halogen-containing gas that contains at least one of Si and Ge, the semiconductor substrate being provided with a member comprising an oxide and consisting mainly of Si; and exposing the surface of the semiconductor substrate to an atmosphere containing at least one of a Si-containing gas not containing halogen and a Ge-containing gas not containing halogen after starting exposure of the surface of the semiconductor substrate to the halogen-containing gas, thereby epitaxially growing a crystal film containing at least one of Si and Ge on the surface.Type: GrantFiled: September 22, 2011Date of Patent: October 8, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Ichiro Mizushima, Shinji Mori, Masahiko Murano, Tsutomu Sato, Takashi Nakao, Hiroshi Itokawa
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Publication number: 20130017674Abstract: Described herein are methods for forming a semiconductor structure. The methods involve forming a doped semiconductor film, amorphizing the doped semiconductor film through ion implantation; and annealing the doped semiconductor film. The ion implantation and the annealing can increase an activation efficiency of the dopant. The ion implantation and the annealing can also reduce a number of crystalline defects in the doped semiconductor film.Type: ApplicationFiled: July 13, 2011Publication date: January 17, 2013Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Inventor: Hiroshi Itokawa
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Publication number: 20120090535Abstract: A method of fabricating a semiconductor device according to one embodiment includes: exposing a surface of a semiconductor substrate to a halogen-containing gas that contains at least one of Si and Ge, the semiconductor substrate being provided with a member comprising an oxide and consisting mainly of Si; and exposing the surface of the semiconductor substrate to an atmosphere containing at least one of a Si-containing gas not containing halogen and a Ge-containing gas not containing halogen after starting exposure of the surface of the semiconductor substrate to the halogen-containing gas, thereby epitaxially growing a crystal film containing at least one of Si and Ge on the surface.Type: ApplicationFiled: September 22, 2011Publication date: April 19, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Ichiro Mizushima, Shinji Mori, Masahiko Murano, Tsutomu Sato, Takashi Nakao, Hiroshi Itokawa
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Patent number: 8043945Abstract: A method of fabricating a semiconductor device according to one embodiment includes: exposing a surface of a semiconductor substrate to a halogen-containing gas that contains at least one of Si and Ge, the semiconductor substrate being provided with a member comprising an oxide and consisting mainly of Si; and exposing the surface of the semiconductor substrate to an atmosphere containing at least one of a Si-containing gas not containing halogen and a Ge-containing gas not containing halogen after starting exposure of the surface of the semiconductor substrate to the halogen-containing gas, thereby epitaxially growing a crystal film containing at least one of Si and Ge on the surface.Type: GrantFiled: March 10, 2009Date of Patent: October 25, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Ichiro Mizushima, Shinji Mori, Masahiko Murano, Tsutomu Sato, Takashi Nakao, Hiroshi Itokawa
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Patent number: 8012858Abstract: A method of fabricating a semiconductor device according to one embodiment includes: removing a native oxide film and adhering silicon nitrides on an area of a Si based substrate in hydrogen gas atmosphere under a condition in which a pressure is a first pressure and a temperature is a first temperature, a silicon nitride-containing member being formed on the Si based substrate, the area being a area not covered by the member; lowering the temperature to a second temperature from the first temperature while maintaining the pressure at the first pressure in hydrogen gas atmosphere; lowering the pressure to a second pressure from the first pressure while maintaining the temperature at the second temperature in hydrogen gas atmosphere; and epitaxially growing a crystal on the area of the Si based substrate in a precursor gas atmosphere after the pressure is lowered to the second pressure, the crystal including at least one of Si and Ge, the precursor gas atmosphere including at least one of hydrogen, Si and Ge.Type: GrantFiled: September 15, 2009Date of Patent: September 6, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masahiko Murano, Ichiro Mizushima, Tsutomu Sato, Shinji Mori, Shuji Katsui, Hiroshi Itokawa
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Patent number: 7986013Abstract: A semiconductor device includes a first semiconductor region having a channel region, and containing silicon as a main component, second semiconductor regions sandwiching the first semiconductor region, formed of SiGe, and applying stress to the first semiconductor region, cap layers provided on the second semiconductor regions, and formed of silicon containing carbon or SiGe containing carbon, and silicide layers provided on the cap layers, and formed of nickel silicide or nickel-platinum alloy silicide.Type: GrantFiled: November 14, 2008Date of Patent: July 26, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Itokawa, Ichiro Mizushima
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Publication number: 20110014781Abstract: According to one embodiment, a method of fabricating a semiconductor device includes forming a first insulator on a semiconductor substrate, forming a first groove on the insulator to expose at least a part of the semiconductor substrate at a bottom of the first groove, forming a first embedding film including at least germanium in the groove, melting the first embedding film by heat treatment, and crystallizing the first embedding film being melted to a single-crystalline film using the semiconductor substrate as a seed.Type: ApplicationFiled: July 15, 2010Publication date: January 20, 2011Inventors: Hiroshi Itokawa, Ichiro Mizushima
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Publication number: 20100327329Abstract: According to one embodiment, a semiconductor device includes a transistor, an element isolation insulating film, and a metal silicide layer. The transistor contains a gate electrode and an epitaxial crystal layer. The epitaxial crystal layer is formed on at least one side of the gate electrode in the semiconductor substrate and includes a facet having a different plane direction from a principal plane of the semiconductor substrate. The element isolation insulating film contains a lower layer and an upper layer. A horizontal distance between the upper layer and the gate electrode is smaller than a horizontal distance between the lower layer and the gate electrode. A part of the upper layer contacts with the facet. The metal silicide layer is formed on an upper surface of the epitaxial crystal layer and on a region of the facet above a contact portion of the facet with the upper layer.Type: ApplicationFiled: June 16, 2010Publication date: December 30, 2010Inventor: Hiroshi ITOKAWA
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Publication number: 20100099241Abstract: A method of fabricating a semiconductor device according to one embodiment includes: removing a native oxide film and adhering silicon nitrides on an area of a Si based substrate in hydrogen gas atmosphere under a condition in which a pressure is a first pressure and a temperature is a first temperature, a silicon nitride-containing member being formed on the Si based substrate, the area being a area not covered by the member; lowering the temperature to a second temperature from the first temperature while maintaining the pressure at the first pressure in hydrogen gas atmosphere; lowering the pressure to a second pressure from the first pressure while maintaining the temperature at the second temperature in hydrogen gas atmosphere; and epitaxially growing a crystal on the area of the Si based substrate in a precursor gas atmosphere after the pressure is lowered to the second pressure, the crystal including at least one of Si and Ge, the precursor gas atmosphere including at least one of hydrogen, Si and Ge.Type: ApplicationFiled: September 15, 2009Publication date: April 22, 2010Inventors: Masahiko MURANO, Ichiro Mizushima, Tsutomu Sato, Shinji Mori, Shuji Katsui, Hiroshi Itokawa
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Publication number: 20100084685Abstract: A semiconductor device includes an SiGe film formed on part of a semiconductor substrate and including a channel region and at least part of source/drain extension regions between which the channel region is positioned, source/drain contact regions formed in a surface area of the semiconductor substrate and brought into contact with the pair of source/drain extension regions, a gate structure having a gate insulation film formed on the SiGe film and a gate electrode formed on the gate insulation film, first sidewall films formed on the SiGe film along side surfaces of the gate structure, second sidewall films formed on the SiGe film along the first sidewall films, third sidewall films formed on the source/drain contact regions along side surfaces of the SiGe film and the second sidewall films, and first silicide films formed on the source/drain contact regions.Type: ApplicationFiled: September 21, 2009Publication date: April 8, 2010Inventors: Hiroshi ITOKAWA, Takashi Fukushima
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Publication number: 20100029053Abstract: A method of manufacturing a semiconductor device for forming an n-type FET has forming an isolation insulating film on a surface of the semiconductor substrate consisting primarily of silicon, the isolation insulating film partitioning a device region of the semiconductor substrate; forming a gate insulating film on the device region of the semiconductor substrate; forming a gate electrode on the gate insulating film; amorphizing regions to be source/drain contact regions adjacent to the gate electrode, of the device region, by ion implanting of one of a carbon cluster ion, a carbon monomer ion and a molecular ion containing carbon into the regions to be the source/drain contact regions; forming an impurity-implanted layer to be the source/drain contact regions by ion implanting at least one of arsenic and phosphorus as an n-type impurity into the amorphized regions; and activating the carbon and the impurity in the impurity-implanted layer by heat treatment.Type: ApplicationFiled: August 3, 2009Publication date: February 4, 2010Inventors: Hiroshi Itokawa, Ichiro Mizushima, Kiyotaka Miyano
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Publication number: 20100006907Abstract: In a FET using a SiGe film as a channel region, dispersion of the Ge concentration in the SiGe film and dispersion of the film thickness of the SiGe film are suppressed. The FET includes: a substrate 101 having silicon as its main component; a trench 104 formed on a substrate 101 formed so as to surround an element region; a SiGe film 107 formed on the substrate 101 in the element region; and a silicon migration prevention layer 106 which is formed on a part 104a of a side wall of the trench 104 and which contains at least one of nitrogen and carbon.Type: ApplicationFiled: June 30, 2009Publication date: January 14, 2010Inventor: Hiroshi ITOKAWA