Patents by Inventor Hiroshi Kono

Hiroshi Kono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200295140
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer; a gate electrode; and a gate insulating layer which is provided between the silicon carbide layer and the gate electrode and includes a first silicon oxide layer and a second silicon oxide layer provided between the first silicon oxide layer and the gate electrode, the first silicon oxide layer having a first nitrogen concentration and a first thickness, the second silicon oxide layer having a second nitrogen concentration lower than the first nitrogen concentration and a second thickness. The second thickness between an end portion of the gate electrode and the silicon carbide layer is greater than the second thickness between a central portion of the gate electrode and the silicon carbide layer.
    Type: Application
    Filed: September 3, 2019
    Publication date: September 17, 2020
    Inventors: Shigeto Fukatsu, Masaru Furukawa, Hiroshi Kono, Takuma Suzuki, Shunsuke Asaba
  • Patent number: 10777675
    Abstract: A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane, a first SiC region of a first conductivity type, second and third SiC regions of a second conductivity type provided between the first SiC region and the first plane, a fourth SiC region of the first conductivity type provided between the second SiC region and the first plane, a fifth SiC region of the first conductivity type provided between the third SiC region and the first plane, a gate electrode provided between the second SiC region and the third SiC region, a gate insulating layer, a sixth SiC region of the second conductivity type provided between the first SiC region and the second SiC region, and a seventh SiC region of the second conductivity type provided between the first SiC region and the third SiC region.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: September 15, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki Ohashi, Ryosuke Iijima, Hiroshi Kono, Tatsuo Shimizu
  • Publication number: 20200279940
    Abstract: A semiconductor device according to an embodiment includes first electrode; second electrode; silicon carbide layer between the first electrode and the second electrode, the silicon carbide layer having first and second plane, the silicon carbide layer including first silicon carbide region of first-conductivity-type, second silicon carbide region and third silicon carbide region between the first silicon carbide region and the first plane, fourth silicon carbide region between the second silicon carbide region and the first plane, the fourth silicon carbide region contacting the first electrode, fifth silicon carbide region between the second silicon carbide region and the third silicon carbide region, the fifth silicon carbide region having a higher first-conductivity-type impurity concentration than the first silicon carbide region, sixth silicon carbide region between the fifth silicon carbide region and the first plane, the sixth silicon carbide region contacting the first electrode; gate electrode facin
    Type: Application
    Filed: September 3, 2019
    Publication date: September 3, 2020
    Inventors: Hiroshi Kono, Teruyuki Ohashi, Masaru Furukawa
  • Patent number: 10741686
    Abstract: A method for manufacturing a semiconductor device according to an embodiment includes implanting impurity ions into a SiC layer in a direction of <10-11>±1 degrees, <10-1-1>±1 degrees, <10-12>±1 degrees, or <10-1-2>±1 degrees.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: August 11, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kono, Tomohiro Nitta
  • Patent number: 10597375
    Abstract: A novel ?-halogen-substituted thiophene compound or a pharmacologically acceptable salt thereof, which has a potent LPA receptor-antagonist activity and is useful as a medicament is provided. A compound represented by the general formula (I) wherein A represents, a phenyl ring, a thiophene ring, or an isothiazole ring; R1 is the same or different, and represents a halogen atom, or a C1-C3 alkyl group; R2 represents a hydrogen atom, or a C1-C6 alkyl group; p represents an integer of 0 to 5; V represents CR3 wherein R3 represents a hydrogen atom, an amino group, a nitro group, or a C1-C3 alkoxy group, or V represents a nitrogen atom; and X represents a halogen atom, or a salt thereof.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: March 24, 2020
    Assignee: UBE INDUSTRIES, LTD.
    Inventors: Noriaki Iwase, Hiroshi Nishida, Makoto Okudo, Masaaki Ito, Shigeyuki Kono, Masaaki Matoyama, Shigeru Ushiyama, Eiji Okanari, Hirofumi Matsunaga, Kenji Nishikawa, Tomio Kimura
  • Publication number: 20200091295
    Abstract: A semiconductor device according to an embodiment includes, a silicon carbide layer having first and second planes; a first electrode on the first plane; a second electrode on the second plane; a first conductivity type first silicon carbide region; second and third silicon carbide regions of a second conductivity type between the first silicon carbide region and the first plane; a first conductivity type fifth silicon carbide region between the first and the second silicon carbide region with higher impurity concentration than the first silicon carbide region; a first conductivity type sixth silicon carbide region between the first and the third silicon carbide region with higher impurity concentration than the first silicon carbide region; a first conductivity type seventh silicon carbide region between the fifth and the sixth silicon carbide region with lower impurity concentration than the fifth and the sixth silicon carbide region; and a gate electrode.
    Type: Application
    Filed: February 12, 2019
    Publication date: March 19, 2020
    Inventors: Teruyuki Ohashi, Hiroshi Kono, Masaru Furukawa
  • Patent number: 10432190
    Abstract: A semiconductor device comprises a first transistor with a silicon carbide layer between the source and the drain electrodes and between the gate and drain electrodes. A diode is formed in the silicon carbide layer. A forward voltage of the diode varies with the voltage applied to the gate electrode of the first transistor. A second transistor is connected to the first transistor. A gate controller applies voltages to gates of the first and second transistor such that the first and second transistors are set to an off-state a first time. The first gate voltage is then increased to an intermediate voltage that is less than a threshold voltage of the first transistor. The intermediate voltage is sufficient to alter the forward voltage of the diode and permit a forward current to flow in the diode. The first gate voltage is then increased to an on-state voltage.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: October 1, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi Kono
  • Patent number: 10394662
    Abstract: A source remote copy configuration in a source storage system is migrated to a destination storage system as a destination remote copy configuration. The destination primary storage apparatus of the destination storage system defines a virtual volume mapped to the primary volume provided by the source primary storage apparatus which is a storage area of the virtual volume; takes over a first identifier of the primary volume to the virtual volume; transfers, when the virtual volume receives an access request, the access request to the source primary storage apparatus to write data in the primary volume; and takes over the first identifier from the virtual volume to another primary volume provided by the destination primary storage apparatus, after completion of copy of data from primary volume of the source primary storage apparatus into primary volume of the destination primary storage apparatus and secondary volume of the destination secondary storage apparatus.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: August 27, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Taiki Kono, Hidenori Suzuki, Kunihiko Nashimoto, Shigeo Homma, Toru Suzuki, Tomohiro Kawaguchi, Hideo Saito, Azusa Jin, Hiroshi Nasu, Keishi Tamura, Shoji Sugino
  • Patent number: 10386925
    Abstract: For providing a tactile sensation regardless of an input position of a user when receiving a pressure at which the tactile sensation is to be provided, The tactile sensation providing apparatus includes: a load detection unit configured to detect a different pressure load depending on a pushed position even when an object presses by a uniform pressure a touch face of a touch sensor to detect a touch input; a tactile sensation providing unit which provides the tactile sensation to the object pressing the touch face of the touch sensor; and a control unit which controls according to the pushed position on the touch face such that the tactile sensation providing unit provides the tactile sensation to the pressing object when the pressing object, applying the uniform pressure, presses any position on the touch face for providing the tactile sensation.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: August 20, 2019
    Assignee: KYOCERA Corporation
    Inventors: Hiroshi Inoue, Kenji Kono, Tomotake Aono, Jun Takeda
  • Patent number: 10355078
    Abstract: A device includes a silicon carbide layer between first and second electrodes. The silicon carbide layer includes first region, second region between the first region and second electrode, and third region between the second region and second electrode. The device includes first and second trenches, through the second and third regions and terminating within the first region, having a layer formed thereon, and spaced by portions of the second and third regions. The silicon carbide layer includes fourth region between the third region and first trench, and fifth region between the third region and second trench. The second region includes a fourth portion between first and second portions, and a fifth portion between second and third portions. The first, second, and third portions have lower impurity than the fourth and fifth portions, and the fourth and fifth portions extend closer to the first electrode than do the other portions.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: July 16, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Kono, Takuma Suzuki
  • Publication number: 20190204438
    Abstract: A measuring device (200) is a device disposed in a mobile body, and includes a measurement unit (202) that scans an object by emitting electromagnetic waves. The measurement unit (202) is controlled by a measurement unit control device (203) including a control unit (204). The control unit (204) sets a scanning range of the measurement unit (202) using information on a position that is a predetermined distance ahead. Specifically, the control unit (204) determines a position that is a predetermined distance ahead of the current position of the mobile body (240), on a predicted course of the mobile body (240). Further, the control unit (204) uses information on the position that is a predetermined distance ahead to set the scanning range of the measurement unit (202).
    Type: Application
    Filed: August 30, 2017
    Publication date: July 4, 2019
    Inventors: Takehiro MATSUDA, Hiroshi AOYAMA, Akira KONO, Eiji KUROKI, Junichi FURUKAWA
  • Patent number: 10186572
    Abstract: A semiconductor device includes first, second, and gate electrodes. A first silicon carbide region of a first type is between the first and second electrodes and between the gate and second electrodes. Second and third silicon carbide regions of a second type are between the first electrode and first silicon carbide region. A portion of the first silicon carbide region is between the second and third silicon carbide regions. A fourth silicon carbide region of the first type is between the first electrode and second silicon carbide region. A fifth silicon carbide region of the first type is between the first electrode and third silicon carbide region. An insulation layer is between the gate electrode and second and third silicon carbide regions and sixth silicon carbide region of the second type. A second portion of the first silicon carbide region is between the second electrode and sixth silicon carbide region.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: January 22, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Kono, Teruyuki Ohashi
  • Patent number: 10074539
    Abstract: A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane; a first electrode having a first region in the SiC layer, the inclination angle of a side surface of the first region being 60 to 85 degrees; a second electrode; a first gate electrode; a second gate electrode facing the first gate electrode; first and second gate insulating layers; a first region of a first conductivity type in the SiC layer; a second region of a second conductivity type between the first region and the first gate insulating layer; a third region of the second conductivity type between the first region and the second gate insulating layer; a sixth region of the second conductivity type between the first region and the first region; and a seventh region of the second conductivity type between the first region and the sixth region.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: September 11, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki Ohashi, Hiroshi Kono, Souzou Kanie, Tatsuo Shimizu
  • Publication number: 20180151365
    Abstract: A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane; a first electrode having a first region in the SiC layer, the inclination angle of a side surface of the first region being 60 to 85 degrees; a second electrode; a first gate electrode; a second gate electrode facing the first gate electrode; first and second gate insulating layers; a first region of a first conductivity type in the SiC layer; a second region of a second conductivity type between the first region and the first gate insulating layer; a third region of the second conductivity type between the first region and the second gate insulating layer; a sixth region of the second conductivity type between the first region and the first region; and a seventh region of the second conductivity type between the first region and the sixth region.
    Type: Application
    Filed: January 23, 2018
    Publication date: May 31, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki OHASHI, Hiroshi KONO, Souzou KANIE, Tatsuo SHIMIZU
  • Publication number: 20180083615
    Abstract: A semiconductor device comprises a first transistor with a silicon carbide layer between the source and the drain electrodes and between the gate and drain electrodes. A diode is formed in the silicon carbide layer. A forward voltage of the diode varies with the voltage applied to the gate electrode of the first transistor. A second transistor is connected to the first transistor. A gate controller applies voltages to gates of the first and second transistor such that the first and second transistors are set to an off-state a first time. The first gate voltage is then increased to an intermediate voltage that is less than a threshold voltage of the first transistor. The intermediate voltage is sufficient to alter the forward voltage of the diode and permit a forward current to flow in the diode. The first gate voltage is then increased to an on-state voltage.
    Type: Application
    Filed: February 28, 2017
    Publication date: March 22, 2018
    Inventor: Hiroshi KONO
  • Publication number: 20180083095
    Abstract: A semiconductor device includes first, second, and gate electrodes. A first silicon carbide region of a first type is between the first and second electrodes and between the gate and second electrodes. Second and third silicon carbide regions of a second type are between the first electrode and first silicon carbide region. A portion of the first silicon carbide region is between the second and third silicon carbide regions. A fourth silicon carbide region of the first type is between the first electrode and second silicon carbide region. A fifth silicon carbide region of the first type is between the first electrode and third silicon carbide region. An insulation layer is between the gate electrode and second and third silicon carbide regions and sixth silicon carbide region of the second type. A second portion of the first silicon carbide region is between the second electrode and sixth silicon carbide region.
    Type: Application
    Filed: February 27, 2017
    Publication date: March 22, 2018
    Inventors: Hiroshi KONO, Teruyuki OHASHI
  • Patent number: 9916981
    Abstract: A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane; a first electrode having a first region in the SiC layer, the inclination angle of a side surface of the first region being 60 to 85 degrees; a second electrode; a first gate electrode; a second gate electrode facing the first gate electrode; first and second gate insulating layers; a first region of a first conductivity type in the SiC layer; a second region of a second conductivity type between the first region and the first gate insulating layer; a third region of the second conductivity type between the first region and the second gate insulating layer; a sixth region of the second conductivity type between the first region and the first region; and a seventh region of the second conductivity type between the first region and the sixth region.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: March 13, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki Ohashi, Hiroshi Kono, Souzou Kanie, Tatsuo Shimizu
  • Patent number: 9882036
    Abstract: A semiconductor device includes first and second electrodes and a silicon carbide layer located between the first and second electrodes. A plurality of gate electrodes is interposed between the first electrode and the silicon carbide layer and extends in a first direction. The silicon carbide layer includes a plurality of spaced apart openings having sidewalls and a base which extend inwardly between the gate electrodes, a first region containing a second conductivity type impurity extending around and under the openings, and a second region containing a second conductivity type impurity interposed between the portion of the first region extending under the base of the openings. The concentration of the second conductivity type impurity is greater in the second region than in the first region. The silicon carbide layer includes a third region containing a first conductivity type impurity extending inwardly of the first region from the sidewall of the openings.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: January 30, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kono, Takuma Suzuki
  • Publication number: 20180025910
    Abstract: A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane; a first electrode having a first region in the SiC layer, the inclination angle of a side surface of the first region being 60 to 85 degrees; a second electrode; a first gate electrode; a second gate electrode facing the first gate electrode; first and second gate insulating layers; a first region of a first conductivity type in the SiC layer; a second region of a second conductivity type between the first region and the first gate insulating layer; a third region of the second conductivity type between the first region and the second gate insulating layer; a sixth region of the second conductivity type between the first region and the first region; and a seventh region of the second conductivity type between the first region and the sixth region.
    Type: Application
    Filed: February 13, 2017
    Publication date: January 25, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki OHASHI, Hiroshi KONO, Souzou KANIE, Tatsuo SHIMIZU
  • Publication number: 20170365709
    Abstract: A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane, a first SiC region of a first conductivity type, second and third SiC regions of a second conductivity type provided between the first SiC region and the first plane, a fourth SiC region of the first conductivity type provided between the second SiC region and the first plane, a fifth SiC region of the first conductivity type provided between the third SiC region and the first plane, a gate electrode provided between the second SiC region and the third SiC region, a gate insulating layer, a sixth SiC region of the second conductivity type provided between the first SiC region and the second SiC region, and a seventh SiC region of the second conductivity type provided between the first SiC region and the third SiC region.
    Type: Application
    Filed: February 13, 2017
    Publication date: December 21, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki OHASHI, Ryosuke IIJIMA, Hiroshi KONO, Tatsuo SHIMIZU