Patents by Inventor Hiroshi Kudo

Hiroshi Kudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8067791
    Abstract: A semiconductor device formed by the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: November 29, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroshi Kudo, Junko Naganuma, Sadahiro Kishii
  • Publication number: 20110183515
    Abstract: A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide film formed on the first copper wiring including carbon.
    Type: Application
    Filed: March 10, 2011
    Publication date: July 28, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hiroshi Kudo, Nobuyuki Ohtsuka, Masaki Haneda, Tamotsu Owada
  • Patent number: 7928476
    Abstract: A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide film formed on the first copper wiring including carbon.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: April 19, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroshi Kudo, Nobuyuki Ohtsuka, Masaki Haneda, Tamotsu Owada
  • Patent number: 7915733
    Abstract: A semiconductor device which includes a first wiring with a via connected to the first wiring, a second wiring connected to the via and a dummy via disposed adjacent to the via at a distance of 100 nm or less and formed on the same layer as the via.
    Type: Grant
    Filed: November 11, 2008
    Date of Patent: March 29, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hiroshi Kudo
  • Patent number: 7679144
    Abstract: The semiconductor device includes a silicon substrate, a device isolation insulating film dividing an active region of the silicon substrate into plural pieces, a gate electrode formed on the active region, a source/drain region which is formed in the active region on both sides of the gate electrode, and which constitutes a MOS transistor of an SRAM memory cell with the gate electrode, an interlayer insulating film formed over each of the active region and the device isolation insulating film, a first hole which is formed in the interlayer isolation insulating film, and which commonly overlaps with two adjacent active regions and the device isolation insulating film between the active regions, and a first conductive plug which is formed in the first hole, and which electrically connects the two active regions.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: March 16, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Hiroshi Kudo, Kenji Ishikawa
  • Publication number: 20100059828
    Abstract: A semiconductor device formed by the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.
    Type: Application
    Filed: November 18, 2009
    Publication date: March 11, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Hiroshi KUDO, Junko NAGANUMA, Sadahiro KISHII
  • Publication number: 20100038792
    Abstract: A semiconductor device includes an insulating layer formed over a semiconductor substrate, the insulating layer including oxygen, a first wire formed in the insulating layer, and a second wire formed in the insulating layer over the first wire and containing manganese, oxygen, and copper, the second wire having a projection portion formed in the insulating layer and extending downwardly but spaced apart from the first wire.
    Type: Application
    Filed: August 4, 2009
    Publication date: February 18, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Hirosato OCHIMIZU, Atsuhiro Tsukune, Hiroshi Kudo
  • Patent number: 7642577
    Abstract: The method for fabricating a semiconductor device comprises the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: January 5, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Hiroshi Kudo, Junko Naganuma, Sadahiro Kishii
  • Publication number: 20090200676
    Abstract: A semiconductor device which includes a first wiring with a via connected to the first wiring, a second wiring connected to the via and a dummy via disposed adjacent to the via at a distance of 100 nm or less and formed on the same layer as the via.
    Type: Application
    Filed: November 11, 2008
    Publication date: August 13, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Hiroshi KUDO
  • Publication number: 20090146309
    Abstract: A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide film formed on the first copper wiring including carbon.
    Type: Application
    Filed: November 20, 2008
    Publication date: June 11, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Hiroshi KUDO, Nobuyuki OHTSUKA, Masaki HANEDA, Tamotsu OWADA
  • Publication number: 20080061445
    Abstract: The semiconductor device includes a silicon substrate, a device isolation insulating film dividing an active region of the silicon substrate into plural pieces, a gate electrode formed on the active region, a source/drain region which is formed in the active region on both sides of the gate electrode, and which constitutes a MOS transistor of an SRAM memory cell with the gate electrode, an interlayer insulating film formed over each of the active region and the device isolation insulating film, a first hole which is formed in the interlayer isolation insulating film, and which commonly overlaps with two adjacent active regions and the device isolation insulating film between the active regions, and a first conductive plug which is formed in the first hole, and which electrically connects the two active regions.
    Type: Application
    Filed: November 12, 2007
    Publication date: March 13, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi KUDO, Kenji ISHIKAWA
  • Publication number: 20080012081
    Abstract: The semiconductor device comprises a plurality of MOS transistors 12 each including a gate electrode 20 formed over a semiconductor substrate 10 with a gate insulating film 18 formed therebetween, and a source diffused layer 28 and a drain diffused layer 34 of a second conductions type arranged with a channel region 36 of a first conduction type therebetween, the source diffused layers 28 and the drain diffused layers 34 of said plural MIS transistors 12 being arranged side by side in the same direction, a pocket region of the first conduction type being formed selectively between the source diffused layer 28 and the channel region 36 of each of the plural MIS transistors 12, and a pocket impurity-not-implanted region being formed between the drain diffused layer 34 and the channel region 36 of each of the plural MIS transistors 12.
    Type: Application
    Filed: September 20, 2007
    Publication date: January 17, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Hiroshi Kudo
  • Patent number: 7163887
    Abstract: A method for fabricating a semiconductor device that prevents the occurrence of bowing and thickness reduction in a dual damascene method. As shown in FIG. 2(B), silicon nitride etching is performed on a semiconductor device in process of fabrication which has a section shown in FIG. 2(A). As a result, part of a copper film is oxidized and changes into oxide. Moreover, a CFx deposit is formed on it. By performing organic insulating film etching by the use of hydrogen plasma in FIG. 2(C), however, the oxide is deoxidized to copper and the CFx deposit is converted into a volatile compound and is removed.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: January 16, 2007
    Assignees: Fujitsu Limited, Tokyo Electron Limited
    Inventors: Hiroshi Kudo, Koichiro Inazawa
  • Patent number: 7064038
    Abstract: The method for fabricating a semiconductor device comprises the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: June 20, 2006
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Kudo, Junko Naganuma, Sadahiro Kishii
  • Patent number: 7041586
    Abstract: A semiconductor device includes a multilayer interconnection structure including an organic interlayer insulation film in which a conductor pattern is formed by a damascene process, wherein the organic interlayer insulation film carries thereon an organic spin-on-glass film.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: May 9, 2006
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Kudo, Masanobu Ikeda, Kenichi Watanabe, Yoshiyuki Ohkura
  • Publication number: 20060035427
    Abstract: The method for fabricating a semiconductor device comprises the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.
    Type: Application
    Filed: October 7, 2005
    Publication date: February 16, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Kudo, Junko Naganuma, Sadahiro Kishii
  • Patent number: D565718
    Type: Grant
    Filed: March 15, 2004
    Date of Patent: April 1, 2008
    Assignee: Fuji Industrial Co., Ltd.
    Inventor: Hiroshi Kudo
  • Patent number: D575861
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: August 26, 2008
    Assignee: Fuji Industrial Co., Ltd.
    Inventor: Hiroshi Kudo
  • Patent number: D580041
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: November 4, 2008
    Assignee: Fuji Industrial Co., Ltd.
    Inventor: Hiroshi Kudo
  • Patent number: D580540
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: November 11, 2008
    Assignee: Fuji Industrial Co., Ltd.
    Inventor: Hiroshi Kudo