Patents by Inventor Hiroshi Kudo

Hiroshi Kudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9456124
    Abstract: A detection device includes a first holding member holding a light receiving element, a second holding member holding an optical system, and first and second fixing members fixing the first and second holding members with the first and second holding members separated from each other, in a direction parallel to a second direction orthogonal to a first direction in which an optical axis of the optical system extends, at least one of a first surface of the first holding member opposite to the second holding member and a second surface of the second holding member opposite to the first holding member has a plane inclined with respect to the first direction, and the first and second fixing members are provided on the inclined plane and disposed between the first and second surfaces.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: September 27, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hiroshi Kudo
  • Publication number: 20150296127
    Abstract: A focus detecting unit that includes a corrector configured to correct a signal output from an image sensor using a first shading correction value when the half-mirror is retreated from an optical path, and to correct the signal using a second shading correction value different from the first shading correction value when the half-mirror is inserted into the optical path, and a focus detector configured to provide a focus detection based on the signal corrected by the corrector.
    Type: Application
    Filed: March 30, 2015
    Publication date: October 15, 2015
    Inventor: Hiroshi Kudo
  • Publication number: 20150235955
    Abstract: A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer including an inorganic film located on the lower layer Cu line and an organic resin film located on the inorganic film, and a via connection part located in a via connection hole running in an up-down direction through the insulating layer in an area where the lower layer Cu line and the upper layer Cu line overlap each other is provided. The via connection part includes a barrier conductive layer located on a part of the lower layer Cu line exposed to a bottom part of the via connection hole and on an inner wall of the via connection hole.
    Type: Application
    Filed: May 5, 2015
    Publication date: August 20, 2015
    Inventors: Hiroshi Kudo, Takamasa Takano
  • Publication number: 20150189156
    Abstract: A detection device includes a first holding member holding a light receiving element, a second holding member holding an optical system, and first and second fixing members fixing the first and second holding members with the first and second holding members separated from each other, in a direction parallel to a second direction orthogonal to a first direction in which an optical axis of the optical system extends, at least one of a first surface of the first holding member opposite to the second holding member and a second surface of the second holding member opposite to the first holding member has a plane inclined with respect to the first direction, and the first and second fixing members are provided on the inclined plane and disposed between the first and second surfaces.
    Type: Application
    Filed: December 22, 2014
    Publication date: July 2, 2015
    Inventor: Hiroshi Kudo
  • Publication number: 20140353829
    Abstract: A semiconductor device includes an insulating layer formed over a semiconductor substrate, the insulating layer including oxygen, a first wire formed in the insulating layer, and a second wire formed in the insulating layer over the first wire and containing manganese, oxygen, and copper, the second wire having a projection portion formed in the insulating layer and extending downwardly but spaced apart from the first wire.
    Type: Application
    Filed: August 14, 2014
    Publication date: December 4, 2014
    Inventors: Hirosato OCHIMIZU, Atsuhiro TSUKUNE, Hiroshi KUDO
  • Patent number: 8836126
    Abstract: A semiconductor device includes an insulating layer formed over a semiconductor substrate, the insulating layer including oxygen, a first wire formed in the insulating layer, and a second wire formed in the insulating layer over the first wire and containing manganese, oxygen, and copper, the second wire having a projection portion formed in the insulating layer and extending downwardly but spaced apart from the first wire.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: September 16, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hirosato Ochimizu, Atsuhiro Tsukune, Hiroshi Kudo
  • Patent number: 8067791
    Abstract: A semiconductor device formed by the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: November 29, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroshi Kudo, Junko Naganuma, Sadahiro Kishii
  • Publication number: 20110183515
    Abstract: A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide film formed on the first copper wiring including carbon.
    Type: Application
    Filed: March 10, 2011
    Publication date: July 28, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Hiroshi Kudo, Nobuyuki Ohtsuka, Masaki Haneda, Tamotsu Owada
  • Patent number: 7928476
    Abstract: A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide film formed on the first copper wiring including carbon.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: April 19, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroshi Kudo, Nobuyuki Ohtsuka, Masaki Haneda, Tamotsu Owada
  • Patent number: 7915733
    Abstract: A semiconductor device which includes a first wiring with a via connected to the first wiring, a second wiring connected to the via and a dummy via disposed adjacent to the via at a distance of 100 nm or less and formed on the same layer as the via.
    Type: Grant
    Filed: November 11, 2008
    Date of Patent: March 29, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hiroshi Kudo
  • Patent number: 7679144
    Abstract: The semiconductor device includes a silicon substrate, a device isolation insulating film dividing an active region of the silicon substrate into plural pieces, a gate electrode formed on the active region, a source/drain region which is formed in the active region on both sides of the gate electrode, and which constitutes a MOS transistor of an SRAM memory cell with the gate electrode, an interlayer insulating film formed over each of the active region and the device isolation insulating film, a first hole which is formed in the interlayer isolation insulating film, and which commonly overlaps with two adjacent active regions and the device isolation insulating film between the active regions, and a first conductive plug which is formed in the first hole, and which electrically connects the two active regions.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: March 16, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Hiroshi Kudo, Kenji Ishikawa
  • Publication number: 20100059828
    Abstract: A semiconductor device formed by the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.
    Type: Application
    Filed: November 18, 2009
    Publication date: March 11, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Hiroshi KUDO, Junko NAGANUMA, Sadahiro KISHII
  • Publication number: 20100038792
    Abstract: A semiconductor device includes an insulating layer formed over a semiconductor substrate, the insulating layer including oxygen, a first wire formed in the insulating layer, and a second wire formed in the insulating layer over the first wire and containing manganese, oxygen, and copper, the second wire having a projection portion formed in the insulating layer and extending downwardly but spaced apart from the first wire.
    Type: Application
    Filed: August 4, 2009
    Publication date: February 18, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Hirosato OCHIMIZU, Atsuhiro Tsukune, Hiroshi Kudo
  • Patent number: 7642577
    Abstract: The method for fabricating a semiconductor device comprises the steps of: forming a dummy electrode 22n and a dummy electrode 22p; forming a metal film 32 on the dummy electrode 22p; conducting a thermal treatment at a first temperature to substitute the dummy electrode 22n with an electrode 34a of a material containing the constituent material of the metal film 32; forming a metal film 36 on the dummy electrode 22n; and conducting a thermal treatment at a second temperature, which is lower than the first temperature and at which an interdiffusion of constituent materials between the electrode 34a and the metal film 36 does not take place, to substitute the second dummy electrode with an electrode 34b of a material containing the constituent material of the metal film 36.
    Type: Grant
    Filed: October 7, 2005
    Date of Patent: January 5, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Hiroshi Kudo, Junko Naganuma, Sadahiro Kishii
  • Publication number: 20090200676
    Abstract: A semiconductor device which includes a first wiring with a via connected to the first wiring, a second wiring connected to the via and a dummy via disposed adjacent to the via at a distance of 100 nm or less and formed on the same layer as the via.
    Type: Application
    Filed: November 11, 2008
    Publication date: August 13, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Hiroshi KUDO
  • Publication number: 20090146309
    Abstract: A semiconductor device has a first insulating film formed over a semiconductor substrate, a first opening formed in the first insulating film, a first manganese oxide film formed along an inner wall of the first opening, a first copper wiring embedded in the first opening, and a second manganese oxide film formed on the first copper wiring including carbon.
    Type: Application
    Filed: November 20, 2008
    Publication date: June 11, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Hiroshi KUDO, Nobuyuki OHTSUKA, Masaki HANEDA, Tamotsu OWADA
  • Patent number: D565718
    Type: Grant
    Filed: March 15, 2004
    Date of Patent: April 1, 2008
    Assignee: Fuji Industrial Co., Ltd.
    Inventor: Hiroshi Kudo
  • Patent number: D575861
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: August 26, 2008
    Assignee: Fuji Industrial Co., Ltd.
    Inventor: Hiroshi Kudo
  • Patent number: D580041
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: November 4, 2008
    Assignee: Fuji Industrial Co., Ltd.
    Inventor: Hiroshi Kudo
  • Patent number: D580540
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: November 11, 2008
    Assignee: Fuji Industrial Co., Ltd.
    Inventor: Hiroshi Kudo