Patents by Inventor Hiroshi Mukainakano

Hiroshi Mukainakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6111388
    Abstract: A charge/discharge control circuit is provided which prevents an abnormally high charging voltage from damaging a secondary cell. The charge/discharge control circuit has an overcharge detecting circuit for detecting whether the secondary cell is in an overcharged state by comparing a divided output voltage of the secondary cell with a reference voltage, a delay circuit for outputting a delayed version of an output of the overcharge detecting circuit delayed by a predetermined delay time, and a high voltage detecting circuit for detecting whether the secondary cell is in a high voltage supplying state by detecting whether a voltage of the secondary cell is more than a predetermined level higher than the overcharge detecting voltage detected by the overcharge detecting circuit. The switch circuit is turned OFF to stop charging of the secondary cell when either the overcharge state or the high voltage supplying state is detected in response to outputs of the delay circuit and the high voltage detecting circuit.
    Type: Grant
    Filed: February 13, 1998
    Date of Patent: August 29, 2000
    Assignee: Seiko Instruments Inc.
    Inventor: Hiroshi Mukainakano
  • Patent number: 6107862
    Abstract: An improved charge pump circuit includes one switch element driven by a ramp waveform to precisely control the output voltage. The circuit includes a switch group having one or more switch elements for transferring a charge to one or more capacitors, a feedback circuit having an error amplifier for amplifying a difference between a divided output voltage and a reference voltage, a compensation circuit for phase compensating the feedback network, an oscillator for generating the ramp waveform, and a control circuit for driving the one or more switch elements. At least one of the switch elements has a resistance that can be adjusted externally and is driven by the ramp waveform such that its resistance varies with time. Accordingly, the charge transferred from a power source to the one or more capacitors can easily be adjusted. When the charge transferred is small, the on-time of the ramp waveform is short and the average value of the resistance is large.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: August 22, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Hiroshi Mukainakano, Kimio Shibata
  • Patent number: 6097177
    Abstract: A charge/discharge control circuit for controlling the charging and discharging of a secondary cell has a voltage dividing circuit for dividing an output voltage of the secondary cell, which may comprise plural cells, an overcharge detection circuit for detecting an overcharge state of the secondary cell, an overdischarge detection circuit for detecting an overdischarge state of the secondary cell, and a control circuit for receiving and processing an output signal of the overcharge detecting circuit and the overdischarge detecting circuit and controlling the switch. In a preferred embodiment, an overcharge reference voltage source used for the overcharge voltage detection circuit is used also as an overdischarge reference voltage source for the overdischarge voltage detection circuit.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: August 1, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Minoru Sudo, Takayuki Takashina, Yoshikazu Kojima, Sadashi Shimoda, Hiroshi Mukainakano
  • Patent number: 6087807
    Abstract: A charge/discharge control circuit is provided for an electric power source apparatus in which a service life is prolonged. A voltage dividing circuit, an overcharge voltage detection circuit, an overdischarge voltage detection circuit and a control circuit are connected in parallel to a secondary cell which is an electric power source, wherein the control circuit detects a condition of the secondary cell from the overcharge/overdischarge voltage detection circuits and outputs a signal Vs for controlling a power supply to an external equipment and a charge by an external power source and controls a switching element provided in series with the voltage dividing circuit and reduces a current which flows through the voltage dividing circuit.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: July 11, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Minoru Sudo, Takayuki Takashina, Yoshikazu Kojima, Sadashi Shimoda, Hiroshi Mukainakano
  • Patent number: 6060863
    Abstract: To improve operation reliability of a charge and discharge control circuit and a chargeable power supply unit using it, and to improve the life of secondary cell. In the charge and discharge control circuit of the chargeable power supply unit, the circuit surely keeps control operation during voltage of the cell falls down because of discharge current and, over-current state and over-discharge state occur at the same time.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: May 9, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Atsushi Sakurai, Hiroshi Mukainakano, Masanao Hamaguchi
  • Patent number: 6054841
    Abstract: A charge/discharge control circuit is provided for an electric power source apparatus in which a service life is prolonged. A voltage dividing circuit, an overcharge voltage detection circuit, an overdischarge voltage detection circuit and a control circuit are connected in parallel to a secondary cell which is an electric power source, wherein the control circuit detects a condition of the secondary cell from the overcharge/overdischarge voltage detection circuits and outputs a signal Vs for controlling a power supply to an external equipment and a charge by an external power source and controls a switching element provided in series with the voltage dividing circuit and reduces a current which flows through the voltage dividing circuit.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: April 25, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Minoru Sudo, Takayuki Takashina, Yoshikazu Kojima, Sadashi Shimoda, Hiroshi Mukainakano
  • Patent number: 6052016
    Abstract: A plurality of combinations of overcurrent detection voltages and delay times are set in a charge and discharge control circuit. Accordingly, a charge and discharge control circuit is formed in which an overcurrent condition having unexpectedly large consumption current, such as a short circuit, does not damage the circuit.
    Type: Grant
    Filed: February 3, 1998
    Date of Patent: April 18, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Kazunari Sugiura, Hiroshi Mukainakano, Masanao Hamaguchi, Takayuki Takahashi
  • Patent number: 5998974
    Abstract: A charge/discharge control circuit has a voltage detector for detecting a voltage level of a secondary cell, a switch connected in series with the secondary cell, and a control circuit connected in parallel with the voltage detector for receiving and processing an output signal of the voltage detector and controlling an impedance of the switch. The voltage detector, the switch and the control circuit are integrated in a single substrate. In a preferred embodiment, the switch comprises an external connection terminal and a second terminal connected to the secondary cell, a first IGFET connected between the first and second terminals, a second IGFET connectected between the first terminal and a substrate electrode of the first IGFET, and a third IGFET connected between the second terminal and the substrate electrode of the first IGFET.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: December 7, 1999
    Assignee: Seiko Instruments Inc.
    Inventors: Minoru Sudo, Takayuki Takashina, Yoshikazu Kojima, Sadashi Shimoda, Hiroshi Mukainakano
  • Patent number: 5990663
    Abstract: To enhance the performance as well as the reliability and safety of a charge/discharge control circuit and a charging type power-supply unit using it, a charge/discharge control circuit 102 is made to have a circuit construction wherein when a load 109 has been connected at a time of a secondary cell 101 being charged and being in a state having been protected from the charging operation, the state of protection from the charging operation is released to thereby make a switch circuit 103 "on" and permit effective performance of the discharging operation while, on the other hand, when a transition occurs from even this state to a state where excess current is consumed from the secondary cell 101 and as a result an excessive amount of current flows through the switch circuit 103, control can be made so that the discharging from the secondary cell 101 may be stopped, thereby enabling avoidance of the FETs from breakage.
    Type: Grant
    Filed: June 12, 1997
    Date of Patent: November 23, 1999
    Assignee: Seiko Instruments Inc.
    Inventor: Hiroshi Mukainakano
  • Patent number: 5982150
    Abstract: A charge/discharge control circuit is provided for an electric power source apparatus in which a service life is prolonged. A voltage dividing circuit, an overcharge voltage detection circuit, an overdischarge voltage detection circuit and a control circuit are connected in parallel to a secondary cell which is an electric power source, wherein the control circuit detects a condition of the secondary cell from the overcharge/overdischarge voltage detection circuits and outputs a signal Vs for controlling a power supply to an external equipment and a charge by an external power source and controls a switching element provided in series with the voltage dividing circuit and reduces a current which flows through the voltage dividing circuit.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: November 9, 1999
    Assignee: Seiko Instruments Inc.
    Inventors: Minoru Sudo, Takayuki Takashina, Yoshikazu Kojima, Sadashi Shimoda, Hiroshi Mukainakano
  • Patent number: 5959436
    Abstract: A charge/discharge control circuit cuts off a current path to stop charging of an abnormal secondary cell when the voltage of the secondary cell is less than the threshold voltage of a MOS transistor.
    Type: Grant
    Filed: February 3, 1998
    Date of Patent: September 28, 1999
    Assignee: Seiko Instruments Inc.
    Inventors: Takayuki Takashina, Shinichi Yoshida, Hiroshi Mukainakano
  • Patent number: 5841265
    Abstract: A charge/discharge control circuit comprises two serially connected electric power sources and two overcharge/overdischarge detection circuits. A control circuit outputs a signal for controlling the charge/discharge of the electric power sources in accordance with signals from the two overcharge/overdischarge detection circuits. An intermediate voltage receiving circuit receives, in accordance with the signal from the control circuit, a voltage at a junction point between the two electric power sources and outputs a signal indicative of a relation of the relative voltage between the two electric power sources.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: November 24, 1998
    Assignee: Seiko Instruments Inc.
    Inventors: Minoru Sudo, Takayuki Takashina, Yoshikazu Kojima, Sadashi Shimoda, Hiroshi Mukainakano
  • Patent number: 5742148
    Abstract: A chargeable power supply which has a charge/discharge control circuit is provided in which the service life of a secondary cell is prolonged. A voltage dividing circuit, an overcharge voltage detection circuit, an overdischarge detection circuit and a control circuit are connected in parallel to the secondary cell. The control circuit receives signals indicating the condition of the secondary cell from the overcharge/overdischarge voltage detection circuits and outputs a signal for controlling a switch circuit for disconnecting the secondary cell from external equipment, or to stop a charging operation by an external power source. The control circuit also controls a switching element provided in series with the voltage dividing circuit and reduces a current which flows through the dividing circuit. A current limiting means is provided to limit the current consumption of the charge/discharge control circuit.
    Type: Grant
    Filed: November 17, 1993
    Date of Patent: April 21, 1998
    Assignee: Seiko Instruments Inc.
    Inventors: Minoru Sudo, Takayuki Takashina, Yoshikazu Kojima, Sadashi Shimoda, Hiroshi Mukainakano
  • Patent number: 5619345
    Abstract: An image sensor of the contact type is comprised of a plurality of image sensor chips arranged linearly with one another. Each chip has an array of picture elements arranged at a given constant pitch which is set slightly smaller than a standard reading pitch in a main scanning direction, thereby ensuring uniform output performance of the image sensor.
    Type: Grant
    Filed: July 16, 1991
    Date of Patent: April 8, 1997
    Assignee: Seiko Instruments Inc.
    Inventors: Satoshi Machida, Yukito Kawahara, Hiroshi Mukainakano, Masahiro Yokomichi
  • Patent number: 5426060
    Abstract: A method of inspecting and a method of manufacturing image sensors formed on a surface of a semiconductor wafer. A semiconductor wafer is provided having image sensors formed on its surface. Grooves are cut at boundaries between image sensors to be inspected, so that each groove has a depth that is smaller than the thickness of the semiconductor wafer. The grooves are cut in the boundaries between the image sensors so that photoN sensing carriers generated in the boundary regions, that are not generated by the image sensor being inspected, do not affect the inspection of the image sensor. The characteristics of the image sensors are inspected before cutting through the semiconductor wafer to form individual image sensors. Thus, in accordance with the present invention, the electrical characteristics of the image sensors can be accurately ascertained either before or after separation from the semiconductor wafer.
    Type: Grant
    Filed: September 2, 1992
    Date of Patent: June 20, 1995
    Assignee: Seiko Instruments Inc.
    Inventors: Yukito Kawahara, Satoshi Machida, Hiroshi Mukainakano, Masahiro Yokomichi, Masato Higashi
  • Patent number: 5329149
    Abstract: An improved image sensor comprises a plurality of photo-sensing elements each comprising an impurity diffusion layer formed in a surface of a semiconductor substrate and arrayed linearly. The photo-sensing elements are of an opposite conductivity type than that of the semiconductor substrate. A transparent insulating film is formed on the photo-sensing elements and the surface of the semiconductor substrate. A non-light transmitting shading film is formed over the transparent insulating film and has photo-sensing windows which overlay a part of each of the photo-sensing elements. The shape and area of each of the photo-sensing elements is equal. The area of each of the photo-sensing windows is equal, but the shape of the first and last photosensing windows is different from that of the remaining photosensing windows. By this arrangement, the amount of photoexcited carriers generated is uniform at all photo-sensing regions, since the area of all photo-sensing windows is equal.
    Type: Grant
    Filed: October 11, 1991
    Date of Patent: July 12, 1994
    Assignee: Seiko Instruments Inc.
    Inventors: Yukito Kawahara, Satoshi Machida, Hiroshi Mukainakano, Masahiro Yokomichi, Masato Higashi
  • Patent number: 5321303
    Abstract: A method for manufacturing a semiconductor device using inclined stage of a dicing saw in order to cut the semiconductor substrate obliquely with respect to the depthwise direction. When a plurality of semiconductor chips diced obliquely are connected, a degree of connecting accuracy is increased, and it is possible to realize a contact-type image sensor of high resolving power and high accuracy.
    Type: Grant
    Filed: April 17, 1992
    Date of Patent: June 14, 1994
    Assignee: Seiko Instruments Inc.
    Inventors: Yukito Kawahara, Hiroshi Mukainakano, Satoshi Machida
  • Patent number: 5198654
    Abstract: The image reading apparatus is of the multi-chip line sensor having a plurality of photoelectric conversion elements connected through corresponding switching elements commonly to every one another. Each group of the commonly connected photoelectric conversion elements outputs on a common line an image signal which is then fed to a sample hold circuit and is thereafter outputted from a single output terminal. By such construction, the image signal from the photoelectric conversion elements is sequentially outputted externally from the single output terminal in the form of output waveshape as held in the sample hold circuit in such manner as to prolong output duration of each bit image signal to thereby enable fast operation of the line sensor.
    Type: Grant
    Filed: March 8, 1991
    Date of Patent: March 30, 1993
    Assignee: Seiko Instruments Inc.
    Inventors: Hiroshi Mukainakano, Yukito Kawahara, Satoshi Machida
  • Patent number: 5151587
    Abstract: The image sensor is comprised of an array of operative bipolar transistors. Another array of optically shielded dummy bipolar transistors are formed adjacently to the operative bipolar transistors. Reset switches are connected to base regions of the operative and dummy bipolar transistors so as to reduce variation in dark image output, to ensure linearity of output signal, and to eliminate image storage.
    Type: Grant
    Filed: January 4, 1991
    Date of Patent: September 29, 1992
    Assignee: Seiko Instruments Inc.
    Inventors: Satoshi Machida, Yukito Kawahara, Hiroshi Mukainakano
  • Patent number: 5146074
    Abstract: The solid state imaging device having an array of bit units formed in a semiconductor substrate. Each bit unit is comprised of a phototransistor having a collector formed of the semiconductor substrate an emitter and a base, a switching transistor of the MOS type having a drain connected to the emitter of the phototransistor, an initializing transistor of the MOS type having a drain connected to the base of the phototransistor, a source receptive of a first reference voltage, and a gate connected to the emitter of the phototransistor, and a resetting transistor of the MOS type having a drain connected to the emitter of the phototransistor, a source receptive of a second reference voltage, and a gate receptive of a reset signal. The resetting transistor operates in the reset signal to enable the initializing transistor to initialize the phototransistor. The switching transistor drives the initialized phototransistor to effect reading of image.
    Type: Grant
    Filed: August 8, 1991
    Date of Patent: September 8, 1992
    Assignee: Seiko Instruments Inc.
    Inventors: Yukito Kawahara, Satoshi Machida, Hiroshi Mukainakano, Masahiro Yokomichi