Patents by Inventor Hiroshi Okumura

Hiroshi Okumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9368781
    Abstract: A storage battery includes a terminal portion for storage batteries having a plurality of bolt insertion holes bored in one or a plurality of directions, a nut insertion opening through which a nut is inserted, a hollow in communication with the bolt insertion holes and the nut insertion opening and the nut having at least one screw hole threaded in a direction coincident with at least one or the plurality of directions. A fixation portion is formed to fix the nut by deforming the terminal portion with the nut being inserted through the nut insertion opening into the hollow and the at least one screw hole of the nut being in communication respectively with the at least one of the plurality of bolt insertion holes.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: June 14, 2016
    Assignee: GS Yuasa International Ltd.
    Inventors: Aya Harada, Eiji Hojo, Yasuhide Nakayama, Shin Osaki, Hiroshi Okumura, Katsuya Noguchi
  • Patent number: 9343416
    Abstract: A semiconductor device of the present invention includes a semiconductor chip; an internal pad for electrical connection formed on a surface of the semiconductor chip; a stress relaxation layer formed on the semiconductor chip and having an opening for exposing the internal pad; a connection pad made of a metal having solder wettability, formed on a part facing the opening of the internal pad and provided with a protruding portion protruding on the stress relaxation layer; a metal flange made of a metal having solder wettability, encompassing the periphery of the protruding portion and formed with a smaller thickness than a protruding amount of the protruding portion onto the stress relaxation layer; and a solder terminal for electrical connection with outside formed on the protruding portion and the metal flange.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: May 17, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Hiroyuki Shinkai, Hiroshi Okumura
  • Publication number: 20160133592
    Abstract: A semiconductor device according to the present invention includes a semiconductor substrate, a pad formed on the semiconductor substrate, a rewiring that is electrically connected to the pad and led to a region outside the pad, a resin layer formed on the rewiring, and an external terminal electrically connected to the rewiring via the resin layer, and the resin layer is formed so as to enter the inside of a slit formed in a region along the periphery of the external terminal in the rewiring.
    Type: Application
    Filed: November 10, 2015
    Publication date: May 12, 2016
    Applicant: ROHM CO., LTD.
    Inventor: Hiroshi OKUMURA
  • Patent number: 9263406
    Abstract: A semiconductor device according to the present invention includes a semiconductor chip having a front surface and a rear surface, a sealing resin layer stacked on the front surface of the semiconductor chip, a post passing through the sealing resin layer in the thickness direction and having a side surface flush with a side surface of the sealing resin layer and a forward end surface flush with a front surface of the sealing resin layer, and an external connecting terminal provided on the forward end surface of the post.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: February 16, 2016
    Assignee: ROHM CO., LTD.
    Inventor: Hiroshi Okumura
  • Publication number: 20160043393
    Abstract: A titanium oxide compound according to the present invention comprises bronze-type titanium oxide or titanium oxide mainly composed of bronze-type titanium oxide, and contains calcium and/or silicon. The titanium oxide compound contains 0.005 to 2.5 mass % inclusive of calcium or 0.15 to 0.55 mass % inclusive of silicon, or contains 0.005 to 1.2 mass % inclusive of calcium and 0.15 to 0.2 mass % inclusive of silicon, or contains 0.005 to 0.1 mass % inclusive of calcium and 0.15 to 0.5 mass % inclusive of silicon.
    Type: Application
    Filed: March 24, 2014
    Publication date: February 11, 2016
    Applicant: KUBOTA Corporation
    Inventors: Kenji HIGASHI, Hiroshi OKUMURA, Yoshiyuki HIRONO
  • Patent number: 9184181
    Abstract: A display substrate includes a gate electrode on a base substrate, an active pattern which overlaps the gate electrode and includes a metal oxide semiconductor, an insulation pattern on the active pattern, a source electrode which contacts the active pattern, a drain electrode which contacts the active pattern and is spaced apart from the source electrode, and a first passivation layer which covers the active pattern and the insulation pattern, and includes fluorine, where the active pattern includes a first portion which directly contacts the insulation pattern and overlaps the gate electrode and the insulation pattern, a second portion which contacts the first passivation layer and has an electrical conductivity substantially larger than that of the first portion, a third portion which contacts the first passivation layer, has an electrical conductivity substantially larger than that of the first portion and is spaced apart from the second portion.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: November 10, 2015
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Je-Hun Lee, Sung-Hoon Yang, Hiroshi Okumura, Jin-Ho Hwang
  • Patent number: 9174854
    Abstract: In a titanium oxide compound according to the present invention, the titanium oxide compound is obtained by eluating potassium of potassium tetratitanate expressed by a general formula K2Ti4O9 and performing thermal processing, and, in an X-ray diffraction spectrum of the potassium tetratitanate obtained by using a Cu—K? ray source, between a peak intensity Ia of a (200) plane, a peak intensity Ic of a (004) plane and a peak intensity Ib of a (31-3) plane, a relationship of Ia>Ib>Ic is satisfied.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: November 3, 2015
    Assignee: Kubota Corporation
    Inventors: Kenji Higashi, Hiroshi Okumura
  • Publication number: 20150279807
    Abstract: A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1, a first electrode pad 21 laminated on the semiconductor chip 1, an intermediate layer 4 having a rectangular shape defined by first edges 49a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1. The first edges 49a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21. The first bump 51 is arranged at one end in the direction x and one end in the direction y.
    Type: Application
    Filed: May 27, 2015
    Publication date: October 1, 2015
    Inventor: Hiroshi OKUMURA
  • Publication number: 20150224742
    Abstract: A metal-resin composite structure (106) is obtained by bonding a metal member (103) and a resin member (105) formed of a thermoplastic resin composition (P) to each other. Regarding six linear portions in total on a surface (110) of the metal member (103) including three arbitrary linear portions which are parallel to each other and another three arbitrary linear portions which are perpendicular to the former three linear portions, a surface roughness measured according to JIS B0601 (corresponding international standard: ISO4287) satisfies the following requirements (1) and (2) at the same time: (1) material ratio of the roughness profile (Rmr) of one or more linear portions at a cutting level of 20% and an evaluation length of 4 mm are lower than or equal to 30%; and (2) ten point average roughnesses (Rz) of all the linear portions at an evaluation length of 4 mm are greater than 2 ?m.
    Type: Application
    Filed: July 17, 2014
    Publication date: August 13, 2015
    Inventors: Goro Inoue, Yuki Kondo, Haruka Takamatsu, Kazuki Kimura, Masaki Misumi, Hiroshi Okumura
  • Patent number: 9091872
    Abstract: A liquid crystal display accommodates a reflective portion with a concavo-convex reflecting pixel electrode for reflecting incident light from the display face side, and a transmissive portion with a transmissive pixel electrode for transmitting light output from the backlight. In a wide viewing angle region, luminance of the reflective portion is greater than the transmissive portion. In other angle regions, luminance of the transmissive portion is greater than the reflective portion. In a wide viewing field mode, the reflective portion and transmissive portion both perform normal display. In the narrow viewing field mode, the transmissive portion performs normal display, while the reflective portion performs cancelling data display, thereby rendering unviewable the display content of the transmissive portion from beyond a certain viewing angle.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: July 28, 2015
    Assignee: NLT Technologies, Ltd.
    Inventors: Jin Matsushima, Hiroshi Okumura, Ken Sumiyoshi
  • Patent number: 9081218
    Abstract: A liquid crystal display device (1) includes: a plurality of groups of scanning lines (Gia) and (Gib) via which gate signals are outputted to a plurality of pixels (PIX); and scanning line driving circuits (5a) and (5b) which generate the gate signals and which are disposed for each separate one of a plurality of groups of scanning lines (Gia) and (Gib), the liquid crystal display device (1) further including potential control circuits (15a) and (15b), placed in front of the scanning line driving circuits (5a) and (5b), respectively which incline, for each separate one of the groups of scanning lines (Gia) and (Gib), falling edges of high-potential signals (VGH1) and (VGH2) in accordance with which the gate signals are generated and which are composed of pulse waves. This prevents luminance unevenness from occurring in each display region.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: July 14, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hiroshi Okumura
  • Patent number: 9070673
    Abstract: A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1, a first electrode pad 21 laminated on the semiconductor chip 1, an intermediate layer 4 having a rectangular shape defined by first edges 49a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1. The first edges 49a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21. The first bump 51 is arranged at one end in the direction x and one end in the direction y.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: June 30, 2015
    Assignee: ROHM CO., LTD.
    Inventor: Hiroshi Okumura
  • Publication number: 20150165661
    Abstract: In a complex of the invention, a resin member made of a resin material including a polyolefin and a metal member are joined together through a primer layer. In addition, the resin member is obtained by molding the resin material by injection, a coexistence layer in which a primer resin material configuring the primer layer and the resin material coexist is formed between the primer layer and the resin member, and a thickness of the coexistence layer is in a range of more than or equal to 5 nm and less than or equal to 50 nm.
    Type: Application
    Filed: March 15, 2013
    Publication date: June 18, 2015
    Applicant: Mitsui Chemicals, Inc.
    Inventors: Hiroshi Okumura, Kiminori Uchida, Kazuki Kimura, Goro Inoue, Takeharu Isaki
  • Patent number: 9018762
    Abstract: An inventive semiconductor device includes: a semiconductor chip; an internal pad provided on a surface of the semiconductor chip for electrical connection; a surface protective film covering the surface of the semiconductor chip and having a pad opening from which the internal pad is exposed; a stress relief layer provided on the surface protective film and having an opening portion through which the internal pad exposed from the pad opening is exposed; a connection pad including an anchor buried in the pad opening and the opening portion and connected to the internal pad, and a projection provided integrally with the anchor as projecting on the stress relief layer, the projection having a width greater than an opening width of the opening portion; and a metal ball provided for external electrical connection as covering the projection of the connection pad.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: April 28, 2015
    Assignee: Rohm Co., Ltd.
    Inventors: Masaki Kasai, Hiroshi Okumura
  • Publication number: 20150069336
    Abstract: A thin film transistor includes a gate electrode on a substrate, a gate insulation layer which covers the gate electrode on the substrate, an oxide semiconductor pattern which is disposed on the gate insulation layer and includes a channel portion superimposed over the gate electrode, and low resistance patterns provided at edges of the channel portion, respectively, and including oxygen vacancies, a channel passivation layer on the oxide semiconductor pattern, a reaction layer which covers the oxide semiconductor pattern and the channel passivation layer, and includes a metal oxide, and a source electrode and a drain electrode which contact the oxide semiconductor pattern.
    Type: Application
    Filed: February 7, 2014
    Publication date: March 12, 2015
    Applicant: Samsung Display Co., LTD.
    Inventors: Hiroshi OKUMURA, Je-Hun LEE, Jin-Hyun PARK
  • Publication number: 20150053970
    Abstract: A display substrate includes a gate electrode on a base substrate, an active pattern which overlaps the gate electrode and includes a metal oxide semiconductor, an insulation pattern on the active pattern, a source electrode which contacts the active pattern, a drain electrode which contacts the active pattern and is spaced apart from the source electrode, and a first passivation layer which covers the active pattern and the insulation pattern, and includes fluorine, where the active pattern includes a first portion which directly contacts the insulation pattern and overlaps the gate electrode and the insulation pattern, a second portion which contacts the first passivation layer and has an electrical conductivity substantially larger than that of the first portion, a third portion which contacts the first passivation layer, has an electrical conductivity substantially larger than that of the first portion and is spaced apart from the second portion.
    Type: Application
    Filed: August 8, 2014
    Publication date: February 26, 2015
    Inventors: Je-Hun LEE, Sung-Hoon YANG, Hiroshi OKUMURA, Jin-Ho HWANG
  • Patent number: 8853062
    Abstract: A laser crystallization device includes a first light source providing a first light and a second light source providing a second light. The device further includes a first lens set receiving the first light to generate a first transmitted light, the first transmitted light having a first profile, the first profile having a first profile error portion and a first non-error portion. The device further includes a second lens set receiving the second light to generate a second transmitted light, the second transmitted light having a second profile, the second profile having a second profile error portion and a second non-error portion, the second profile error portion corresponding to the first non-error portion, the second non-error portion corresponding to the first profile error portion. The device further includes an optical system combining the first transmitted light with the second transmitted light.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: October 7, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Hiroshi Okumura
  • Patent number: 8817202
    Abstract: To suppress malshaping in a lenticular lens sheet formed by using ultraviolet curing resin, which is caused due to an increase in the aspect ratio of cylindrical lenses and anisotropy of curing contraction. Notch sections are provided to the cylindrical lenses for sectioning the cylindrical lenses in a pseudo manner in the major axis direction (extending direction) of the cylindrical lenses so as to suppress the anisotropy of the curing contraction of the resin.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: August 26, 2014
    Assignee: NLT Technologies, Ltd.
    Inventor: Hiroshi Okumura
  • Publication number: 20140212739
    Abstract: Provided is a terminal portion for storage batteries that allows a nut to be fixed thereto easily and reliably so that the nut does not fall therefrom, and that allows a bolt to be inserted into the nut by selecting either one of the upper surface or the front surface, or two or more points at the same time when connecting an external lead wire to a storage battery even if the nut is fixed to the terminal portion, and a storage battery including such a terminal portion for storage batteries.
    Type: Application
    Filed: June 18, 2012
    Publication date: July 31, 2014
    Applicant: GS YUASA INTERNATIONAL LTD.
    Inventors: Aya Harada, Eiji Hojo, Yasuhide Nakayama, Shin Osaki, Hiroshi Okumura, Katsuya Noguchi
  • Patent number: 8746916
    Abstract: A showcase comprising an illumination apparatus which includes a shade member constituted of a light-transmitting front wall positioned on the side of the light emitting surfaces of LED elements, and a back wall positioned on the side of a substrate provided with the LED elements, the front wall comprising a curved portion having an arc-like section and a pair of flat portions extended continuously from both ends of the curved portion to intersect with the back wall at an acute angle, corner portions where the flat portions intersect with the back wall being a pair of engaging portions; and a holder provided with a plurality of engagement portions and the like with which the engaging portions are disengageably engaged.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: June 10, 2014
    Assignee: SANYO Electric Co., Ltd.
    Inventors: Tetsuya Oketani, Hiroshi Okumura, Yoichi Amari