Patents by Inventor Hiroshi Shinohara

Hiroshi Shinohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190252432
    Abstract: An imaging device includes pixels each including a photoelectric converter that generates charges by photoelectric conversion, a first transfer transistor that transfers charges of the photoelectric converter to a first holding portion, a second transfer transistor that transfers charges of the first holding portion to a second holding portion, and an amplifier unit that outputs a signal based on charges held by the second holding portion. The first transfer transistor is configured to form a potential well for the charges between the photoelectric converter and the first holding portion when the first transistor is in an on-state. The maximum charge amount QPD generated by the photoelectric converter during one exposure period, a saturation charge amount QMEM_SAT of the first holding portion, and the maximum charge amount QGS that can be held in the potential well are in a relationship of: QPD<QGS?QMEM_SAT.
    Type: Application
    Filed: January 28, 2019
    Publication date: August 15, 2019
    Inventors: Yusuke Onuki, Mahito Shinohara, Hajime Ikeda, Takafumi Miki, Hiroshi Sekine
  • Publication number: 20190251410
    Abstract: To enhance reliability to enable use of all of a plurality of IC-chip-based applications, transmission means of an IC chip support terminal transmits, to an IC chip management server, a registration request for each of a plurality of memory areas respectively corresponding to a plurality of IC-chip-based applications for using an IC chip which is enabled to perform wireless communication. Reception means receives registration instructions for the respective memory areas, each of which is transmitted by the IC chip management server in response to the registration request. Registration means executes processes for registering the respective memory areas in the IC chip successively or in parallel based on the registration instructions. Initial setting means performs an initial setting on each of the registered memory areas when all the plurality of memory areas have been registered in the IC chip.
    Type: Application
    Filed: October 27, 2016
    Publication date: August 15, 2019
    Inventor: Hiroshi SHINOHARA
  • Patent number: 10381084
    Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: August 13, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
  • Patent number: 10364888
    Abstract: A control device for a continuously variable transmission includes: a line pressure generating-section configured to generate a line pressure; a pilot valve configured to supply a pilot pressure regulated so as not to exceed a first predetermined pressure when the line pressure exceeds the first predetermined pressure; a control section configured to generate the clamping forces by controlling the pilot pressure; a line pressure increase section configured to increase the line pressure to be greater than the first predetermined pressure when the control to increase the line pressure is performed when the line pressure is lower than the first predetermined pressure.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: July 30, 2019
    Assignees: JATCO LTD, NISSAN MOTOR CO., LTD.
    Inventors: Tomoaki Honma, Yuta Suzuki, Itaru Shinohara, Hiroshi Sekiya, Hiromu Ogino
  • Publication number: 20190227195
    Abstract: The present invention aims to provide an optical layered body that has excellent interlayer adhesiveness, particularly even in outdoor use, and also has highly excellent anti-blocking properties. The present invention relates to an optical layered body including: a substrate film; a hard coat layer containing silica fine particles on at least one surface of the substrate film; and a dry film layer on a surface of the hard coat layer opposite to the substrate film side surface of the hard coat layer, wherein the silica fine particles are exposed on the dry film layer side surface of the hard coat layer; the dry film layer is directly formed on the surface of the hard coat layer on which the silica fine particles are exposed; the hard coat layer before the formation of the dry film layer has projections and depressions on the surface on which the dry film layer is to be formed; the hard coat layer has an average silica fine particle abundance in ten 0.2 ?m×0.
    Type: Application
    Filed: July 10, 2017
    Publication date: July 25, 2019
    Applicants: Dai Nippon Printing Co., Ltd., Dexerials Corporation
    Inventors: Tomoyuki HORIO, Masataka NAKASHIMA, Hiroshi NAKAMURA, Takahisa NOMURA, Seiji SHINOHARA, Kiyotaka MATSUI, Kentaro OSHIMA, Satoshi KUBOYAMA, Yukihiro ONO
  • Publication number: 20190147835
    Abstract: An upright piano includes an internal space enclosed by a case including an upper front board disposed above a key bed and a lower front board disposed below the key bed, and a resonance tube in which a hollow region having an opening is formed and that is disposed in the internal space, in which the opening is disposed at the left end of the lower end of the upper front board or the upper end of the lower front board, or at the right end of the lower end of the upper front board or the upper end of the lower front board.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 16, 2019
    Inventors: Keiichi FUKATSU, Azumi YOSHIDA, Hiroshi KOMADA, Hitoshi IZUTANI, Taishi SHINOHARA
  • Patent number: 10288903
    Abstract: A progressive addition lens includes a portion having a power for viewing a near field, a portion having a power for viewing a distance field further than the near field, and an portion connecting the distance portion and the near portion. The progressive addition lens includes an aspherical object-side surface and an aspherical eyeball-side surface and is formed in rotational symmetry with respect to a center of design of the progressive addition lens. The object-side surface includes a first stable region formed in rotational symmetry with respect to the center of design and including the center of design, and an aspherical region arranged outside of the first stable region to contact the first stable region and formed in rotational symmetry with respect to the center of design. A PV value (Peak to Valley) of a mean surface refractive power in the first stable region is 0.12 D or less.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 14, 2019
    Assignee: HOYA LENS THAILAND LTD.
    Inventors: Tadashi Kaga, Toshihide Shinohara, Ayumu Ito, Hiroshi Asami
  • Patent number: 10268176
    Abstract: To provide a machine tool and a control device for the machine tool that can smoothly cut a workpiece while segmenting chips by feeding a cutting tool in a feed direction while reciprocally vibrating the cutting tool along the feed direction on the basis of a condition set by a user. The machine tool (100) or the control device (C) includes the control section (C1) that determines a number of rotations of the relative rotation and a number of vibrations of the reciprocal vibration per rotation of the relative rotation when the workpiece (W) is machined in accordance with a vibration frequency dependent on a period in which an operating instruction can be executed.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: April 23, 2019
    Assignees: Citizen Watch Co., Ltd., Citizen Machinery Co., Ltd.
    Inventors: Kazuhiko Sannomiya, Hitoshi Matsumoto, Takanori Shinohara, Hiroshi Shinohara, Toshinari Oyama, Nobuyoshi Imasaki
  • Publication number: 20180345434
    Abstract: In a machine tool, under user set conditions, a cutting tool is fed in a feeding direction while the cutting tool is moved repetitively to cut a workpiece smoothly while separating chips easily. In the machine tool and a control apparatus thereof, control means is configured to set the number of rotations of relative rotation for executing machining of a workpiece, and the number of repetitions of repetitive movement during one rotation of the relative rotation in accordance with a repetitive movement frequency attributable to a cycle during which an operation instruction can be issued.
    Type: Application
    Filed: September 7, 2016
    Publication date: December 6, 2018
    Inventors: Takaichi Nakaya, Kazuhiko Sannomiya, Hiroshi Shinohara
  • Publication number: 20180342300
    Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
    Type: Application
    Filed: August 7, 2018
    Publication date: November 29, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
  • Patent number: 10074434
    Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: September 11, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
  • Publication number: 20180175055
    Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.
    Type: Application
    Filed: February 12, 2018
    Publication date: June 21, 2018
    Inventors: Toshifumi MINAMI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA, Hideyuki KAMATA, Teppei HIGASHITSUJI
  • Publication number: 20180108418
    Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
    Type: Application
    Filed: October 23, 2017
    Publication date: April 19, 2018
    Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
  • Patent number: 9947620
    Abstract: According to one embodiment, a semiconductor memory device includes a wiring layer, an insulating layer, a contact plug, a pillar and a pad. The wiring layer is electrically connected to a memory cell. The insulating layer is provided on the wiring layer. The contact plug is provided in the insulating layer and is electrically connected to an end of the wiring layer. The pillar is provided through the wiring layer and the insulating layer which are located between the memory cell and the contact plug. The pad is electrically connected to one end of the pillar.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: April 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroshi Shinohara
  • Publication number: 20180085677
    Abstract: A mist generating device including a vibrating plate which vibrates at a high frequency and a liquid supply mechanism for supplying a conductive liquid such as water to the vibrating plate and generating a mist by bringing the liquid supplied through the liquid supply mechanism into contact with the vibrating plate for atomization, the mist generating device further including liquid-contact detecting unit for detecting presence of contact of the liquid with the vibrating plate; and protective operation performing unit for performing a protective operation for preventing idle vibration of the vibrating plate when the liquid-contact detecting unit detects non-contact of the liquid with the vibrating plate.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 29, 2018
    Applicant: TOMY COMPANY, LTD.
    Inventors: Shima ATSUZAWA, Hiroshi SHINOHARA, Mamoru SUZUKI, Saburo WATANABE
  • Patent number: 9893078
    Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: February 13, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Toshifumi Minami, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara, Hideyuki Kamata, Teppei Higashitsuji
  • Patent number: 9799403
    Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: October 24, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
  • Patent number: 9791846
    Abstract: To include an analysis processing unit that obtains a movement command for moving on a movement path in a machining program, and vibration conditions for vibrating along the movement path, a command-movement-amount calculation unit that calculates a command-movement amount per unit time, a vibrational-movement-amount calculation unit that uses the vibration conditions to calculate a vibrational-movement amount per unit time at a time corresponding to the movement command, and a movement-amount combining unit that combines the command-movement amount with the vibrational-movement amount to calculate a combined movement amount, and that acquires a movement amount within the unit time such that a position, which has moved from a reference position for calculating the combined movement amount by the combined movement amount, is located on the movement path.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: October 17, 2017
    Assignees: Mitsubishi Electric Corporation, CITIZEN WATCH CO., LTD., CITIZEN MACHINERY CO., LTD.
    Inventors: Mitsuo Watanabe, Masakazu Sagasaki, Junichi Kamata, Hiroshi Shinohara, Hajime Matsumaru, Hitoshi Matsumoto, Takanori Shinohara, Akihiko Shinohara, Shigeo Yanagidaira
  • Publication number: 20170271263
    Abstract: According to one embodiment, a semiconductor memory device includes a wiring layer, an insulating layer, a contact plug, a pillar and a pad. The wiring layer is electrically connected to a memory cell. The insulating layer is provided on the wiring layer. The contact plug is provided in the insulating layer and is electrically connected to an end of the wiring layer. The pillar is provided through the wiring layer and the insulating layer which are located between the memory cell and the contact plug. The pad is electrically connected to one end of the pillar.
    Type: Application
    Filed: March 13, 2017
    Publication date: September 21, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi SHINOHARA
  • Patent number: 9768189
    Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: September 19, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroshi Shinohara, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Toshifumi Minami, Hiroyuki Maeda, Shinji Saito, Hideyuki Kamata