Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

Abstract: To include an analysis processing unit that obtains a movement command for moving on a movement path in a machining program, and vibration conditions for vibrating along the movement path, a command-movement-amount calculation unit that calculates a command-movement amount per unit time, a vibrational-movement-amount calculation unit that uses the vibration conditions to calculate a vibrational-movement amount per unit time at a time corresponding to the movement command, and a movement-amount combining unit that combines the command-movement amount with the vibrational-movement amount to calculate a combined movement amount, and that acquires a movement amount within the unit time such that a position, which has moved from a reference position for calculating the combined movement amount by the combined movement amount, is located on the movement path.

Abstract: According to one embodiment, a semiconductor memory device includes a wiring layer, an insulating layer, a contact plug, a pillar and a pad. The wiring layer is electrically connected to a memory cell. The insulating layer is provided on the wiring layer. The contact plug is provided in the insulating layer and is electrically connected to an end of the wiring layer. The pillar is provided through the wiring layer and the insulating layer which are located between the memory cell and the contact plug. The pad is electrically connected to one end of the pillar.

Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.

Abstract: The present invention provides a power-supply management device which can efficiently connect and disconnect power supply to an electric-powered section, and a machine tool including the power-supply management device. The power-supply management device (101) detects a synchronization command of a control program, and compares an operation time of the electric-powered section between synchronizations in each control system which is a synchronization target by the synchronization command on the basis of the detected synchronization command. Then, the power-supply management device (101) disconnects the power supply to the electric-powered section belonging to the control system except the control system having the maximum operation time of the electric-powered section between the synchronizations, and restarts the power supply at the end of the synchronization in each control system.

Abstract: The present invention provides a power-supply management device which can efficiently connect and disconnect power supply to an electric-powered section, and a machine tool including the power-supply management device. The power-supply management device (101) detects a synchronization command of a control program, and compares an operation time of the electric-powered section between synchronizations in each control system which is a synchronization target by the synchronization command on the basis of the detected synchronization command. Then, the power-supply management device (101) disconnects the power supply to the electric-powered section belonging to the control system except the control system having the maximum operation time of the electric-powered section between the synchronizations, and restarts the power supply at the end of the synchronization in each control system.

Abstract: To provide a machine tool and a control device for the machine tool that can smoothly cut a workpiece while segmenting chips by feeding a cutting tool in a feed direction while reciprocally vibrating the cutting tool along the feed direction on the basis of a condition set by a user. The machine tool (100) or the control device (C) includes the control section (C1) that determines a number of rotations of the relative rotation and a number of vibrations of the reciprocal vibration per rotation of the relative rotation when the workpiece (W) is machined in accordance with a vibration frequency dependent on a period in which an operating instruction can be executed.

Abstract: A semiconductor memory device includes a first word line that is provided above a semiconductor substrate, a second word line that is provided above the first word line, a plurality of semiconductor pillars that are provided on the semiconductor substrate, and pass through the first and second word lines, and first and second plugs that are provided so that the plurality of semiconductor pillars are interposed therebetween. The semiconductor substrate includes an insulating region that is provided deeper than a bottom of the first plug relative to a surface of the semiconductor substrate, between the first plug and one of the semiconductor pillars.

Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

Abstract: A semiconductor memory device includes first and second memory cell transistors, first and second word lines electrically connected to the first and second memory cell transistors, respectively, first and second transfer transistors. The first and second transistors are electrically connected to the first and second word lines, respectively. The sizes of the first transistor and the second transistor are different.

Abstract: According to one embodiment, a non-volatile memory device includes a first stacked electrode provided above a underlying layer, a second stacked electrode juxtaposed with the first stacked electrode above the underlying layer, a plurality of first semiconductor layers piercing the first stacked electrode in a direction perpendicular to the underlying layer, and a second semiconductor layer piercing the second stacked electrode in a direction perpendicular to the underlying layer. The device further includes a memory film provided between the first stacked electrode and the first semiconductor layers, and between the second stacked electrode and the second semiconductor layer, and a link part provided between the underlying layer and the first stacked electrode, and between the underlying layer and the second stacked electrode. The link part is electrically connected to one end of each of the first semiconductor layers and one end of the second semiconductor layer.

Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.

Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.

Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.

Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.

Abstract: To include an analysis processing unit that obtains a movement command for moving on a movement path in a machining program, and vibration conditions for vibrating along the movement path, a command-movement-amount calculation unit that calculates a command-movement amount per unit time, a vibrational-movement-amount calculation unit that uses the vibration conditions to calculate a vibrational-movement amount per unit time at a time corresponding to the movement command, and a movement-amount combining unit that combines the command-movement amount with the vibrational-movement amount to calculate a combined movement amount, and that acquires a movement amount within the unit time such that a position, which has moved from a reference position for calculating the combined movement amount by the combined movement amount, is located on the movement path.

Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

Abstract: A semiconductor memory device includes first and second memory cell transistors, first and second word lines electrically connected to the first and second memory cell transistors, respectively, first and second transfer transistors. The first and second transistors are electrically connected to the first and second word lines, respectively. The sizes of the first transistor and the second transistor are different.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a stacked body including a plurality of electrode layers and a plurality of first insulating layers; a first channel body layer penetrating the stacked body; a memory film; an interlayer insulating film provided on the stacked body; a selection gate electrode provided on the interlayer insulating film; a second channel body layer penetrating the selection gate electrode and the interlayer insulating film and connected to the first channel body; a gate insulating film provided between the selection gate electrode and the second channel body layer; a second insulating layer provided on the gate insulating film and on the selection gate electrode; a contact layer provided on the second insulating layer; and a diffusion layer provided between the contact layer and the second insulating layer and connected to the second channel body layer and the contact layer.