Abstract: A data writing method is disclosed. In a memory system comprising a NAND flash memory and a controller which controls the memory, the memory system storing data provided from a host to the NAND flash memory, the data writing method comprises a steps of specifying a column address in which a column failure which has occurred in the NAND flash memory by the controller, and a step of, during writing into the NAND flash memory, writing data of a first logic level into a memory cell which corresponds to the specified column address regardless of write data provided from the controller.

Abstract: A semiconductor device includes an interface which executes an interfacing process with a semiconductor memory, and a circuit which performs control to write serial data to the semiconductor memory while skipping a position of a defective column on the semiconductor memory.

Abstract: A memory card includes a controller and a nonvolatile semiconductor memory. The controller manages a correspondence between a first address in a semiconductor memory of a first erase block size and a second address in a semiconductor memory of a second erase block size other than the first erase block size. The nonvolatile semiconductor memory is a memory of the second erase block size. The controller executes access to the nonvolatile semiconductor memory by the second address.

Abstract: A first face detecting section detects the face of a passerby based on an image obtained from a first camera set to be easily recognized by the passerby. A second face detecting section detects the face of the passerby based on an image obtained from a second camera set so that the camera will be difficult to be recognized by the passerby. A classifying section classifies the passerby based on the detection results of the faces by the first and second face detecting sections and adjusts a threshold value for authentication based on the classification result. The face collating section calculates the similarity between the face of the passerby and each of faces of registrants and determines whether the passerby is a registrant or not according to whether the degree of calculated similarity is not lower than the adjusted threshold value for authentication.

Abstract: A memory controller for writing data in a first semiconductor memory including a plurality of memory cells having series-connected current paths and charge storage layers includes a host interface which configured to be receivable of first data from a host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with the state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes the first and second data in the first semiconductor memory. When writing the second data, the arithmetic unit does not select a word line adjacent to a select gate line, and selects a word line not adjacent to the select gate line.

Abstract: An integrated semiconductor memory device for use within an integrated USB memory apparatus has a controller, a flash memory in communication with the controller, a USB interface circuit in communication with the memory controller, and an integrated circuit package for maintaining at least one of the controller, the flash memory, and the USB interface within the physical dimensions of a USB connector of the USB memory apparatus.

Abstract: A data writing method is disclosed. In a memory system comprising a NAND flash memory and a controller which controls the memory, the memory system storing data provided from a host to the NAND flash memory, the data writing method comprises a steps of specifying a column address in which a column failure which has occurred in the NAND flash memory by the controller, and a step of, during writing into the NAND flash memory, writing data of a first logic level into a memory cell which corresponds to the specified column address regardless of write data provided from the controller.

Abstract: A memory device comprises a controller having an interface and an MPU, and configured to enable transferring a device driver for a second access mode via the interface in a first access mode, the second access mode differently defined from the first access mode, and a semiconductor memory with the device driver stored thereon.

Abstract: A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device.

Abstract: A nonvolatile semiconductor memory controller has a plurality of word lines and a plurality of memory cells. Each memory cell is connected to a corresponding one of the word lines, and each memory cell has N threshold voltages, where N is a natural number of 4 or greater. The plurality of memory cells constitutes a plurality of pages, the same data is written in each of the pages when writing in the nonvolatile memory, and only part of the pages to which the same data is written is accessed when reading out the nonvolatile memory.

Abstract: An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program code is stored in the first storage area, and user data is stored in the second storage area. The apparatus also includes a volatile memory to which the program code is transferred from the multi-valued NAND nonvolatile memory. The apparatus further includes a CPU connected to the volatile memory and configured to operate based on the program code transferred to the volatile memory.

Abstract: In a memory cell array, a plurality of memory cells each of which stores a plurality of bits are connected to a plurality of word lines and a plurality of bit lines and are arranged in a matrix. Control portions read a threshold level of a second memory cell adjacent to a first memory cell in the memory cell array, determine a correction level according to the threshold level read from the second memory cell, add the determined correction level to a read level of the first memory cell, and then read the threshold level of the first memory cell. A storage portion stores the correction level.

Abstract: A method of writing data to a semiconductor memory device with memory cells, each of which stores data defined by threshold voltage thereof in a non-volatile manner, the device having first and second memory cells disposed adjacent to each other to be sequentially written in this order, the method including: performing a first data write operation for writing data defined by a threshold voltage lower than a desired threshold voltage into the first memory cell; performing a second data write operation for writing data into the second memory cell; and performing a third data writing operation for writing data defined by the desired threshold voltage into the first memory cell.

Abstract: A person recognizing apparatus inputs a face image of a person subject to recognition through a camera and obtains the similarity of this input face image with the registered information stored in the registered information memory pre-storing face images of recognized persons by collating them by the recognizer. Therefore, in this person recognizing apparatus to recognize a said person based on the obtained similarity, a registered information updating unit judges whether the similarity obtained by a recognizer is within a prescribed updating range and updates a registered information stored in the registered information memory based on the face image input by the camera based on being judged as the similarity is in the prescribed updating range.

Abstract: A nonvolatile semiconductor memory package includes a memory device having a memory cell array including a plurality of nonvolatile semiconductor memory cells, a control portion configured to control the memory device, a network interface connectable to a network, a file management portion connected to the network interface configured to manage a relationship between a data file given from the network and an address of the memory cell array, and a memory interface connected to the file management portion configured to convert a signal given from the network to a signal that is capable of being used at the control portion. The package is wrapped by an insulating material.

Abstract: A person identification device obtains information including biometric information of a person, detects the biometric information of at least one person from the obtained information, collates each detected biometric information with the biometric information of at least one registrant associated with group information and stored in a storage unit to thereby identify the person having the biometric information detected from the obtained information, classifies a plurality of successively identified persons into group candidates based on predetermined conditions, divides the persons of the group candidates into groups based on the group information of each person stored in the storage unit, and outputs a grouping result to an external device.

Abstract: A method of writing data to a semiconductor memory device with memory cells, each of which stores data defined by threshold voltage thereof in a non-volatile manner, the device having first and second memory cells disposed adjacent to each other to be sequentially written in this order, the method including: performing a first data write operation for writing data defined by a threshold voltage lower than a desired threshold voltage into the first memory cell; performing a second data write operation for writing data into the second memory cell; and performing a third data writing operation for writing data defined by the desired threshold voltage into the first memory cell.

Abstract: A plurality of memory cells each storing n values (n is a natural number which is not smaller than 3) are arranged in a matrix form in a memory cell array, and each memory cell is connected with a word line and a bit line. Each memory cell stores the n-valued data by a first write operation and a second write operation. A read section sets a potential of a word line, and reads data from a memory cell in the memory cell array. If data read by the read section and written in the second write operation includes an uncorrectable error, a control section changes a potential of a word line supplied to the read section when reading data written in the first write operation.

Abstract: When authentication data of a person O to be authenticated is registered as dictionary data, this authentication data of the person to be authenticated is acquired and collated with the registered dictionary data. In accordance with the collation result, the dictionary data is updated.

Abstract: A memory system includes a ferroelectric memory formed by arranging a plurality of memory cells having a ferroelectric capacitor and cell transistor, a flash EEPROM formed by arranging a plurality of memory cells having a floating gate and capable of electrically erasing and writing data, a control circuit configured to control the ferroelectric memory and flash EEPROM, and an interface circuit configured to communicate with the outside. The flash EEPROM stores data. The ferroelectric memory stores at least one of root information for storing the data, directory information, the file name of the data, the file size of the data, file allocation table information storing the storage location of the data, and the write completion time of the data.