Patents by Inventor Hiroshi Sukegawa

Hiroshi Sukegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM
    Publication number: 20120179865
    Abstract: A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device.
    Type: Application
    Filed: March 22, 2012
    Publication date: July 12, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yasuo KUDO, Hiroshi Sukegawa, Kazuya Kawamoto
  • CARD-SHAPED ELECTRONIC DEVICE, COMMUNICATION TERMINAL AND AUTHENTICATION METHOD
    Publication number: 20120162474
    Abstract: A memory card of an embodiment has an external connection terminal configured to be connected to a card connection terminal of a digital camera having an image pickup unit, a communication unit configured to transmit and receive data wirelessly to and from another digital camera, an image recognition unit configured to extract a characteristic from a recognition image, and a CPU configured to permit subsequent transmission and reception of data to and from the other digital camera when a characteristic of a first recognition image photographed by the image pickup unit and a characteristic of a second recognition image transmitted from the other digital camera correspond to each other.
    Type: Application
    Filed: September 16, 2011
    Publication date: June 28, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi SUKEGAWA
  • IMAGE SEARCH APPARATUS AND IMAGE SEARCH METHOD
    Publication number: 20120140982
    Abstract: According to one embodiment, an image search apparatus includes, an image input module which is input with an image, an event detection module which detects events from the input image input by the image input module, and determines levels, depending on types of the detected events, an event controlling module which retains the events detected by the event detection module, for each of the levels, and an output module which outputs the events retained by the event controlling module, for each of the levels.
    Type: Application
    Filed: September 14, 2011
    Publication date: June 7, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Sukegawa, Osamu Yamaguchi
  • Microprocessor boot-up controller connected to a processor and NAND flash memory for controlling the boot-up of a computer device
    Patent number: 8171281
    Abstract: An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program code is stored in the first storage area, and user data is stored in the second storage area. The apparatus also includes a volatile memory to which the program code is transferred from the multi-valued NAND nonvolatile memory. The apparatus further includes a CPU connected to the volatile memory and configured to operate based on the program code transferred to the volatile memory.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: May 1, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Sukegawa, Kenji Sakaue, Hitoshi Tsunoda
  • Nonvolatile memory system, and data read/write method for nonvolatile memory system
    Patent number: 8161230
    Abstract: A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: April 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Kudo, Hiroshi Sukegawa, Kazuya Kawamoto
  • NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM
    Publication number: 20120072649
    Abstract: A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device.
    Type: Application
    Filed: September 19, 2011
    Publication date: March 22, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasuo KUDO, Hiroshi Sukegawa, Kazuya Kawamoto
  • Memory controller
    Patent number: 8107301
    Abstract: A memory controller for writing data in a first semiconductor memory including a plurality of memory cells having series-connected current paths and charge storage layers includes a host interface which configured to be receivable of first data from a host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with the state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes the first and second data in the first semiconductor memory. When writing the second data, the arithmetic unit does not select a word line adjacent to a select gate line, and selects a word line not adjacent to the select gate line.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: January 31, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Sukegawa, Takeshi Nakano
  • MEMORY DEVICE INCLUDING MEMORY CONTROLLER
    Publication number: 20110296278
    Abstract: A memory device includes a semiconductor memory including a plurality of memory cells, and a controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and are to be stored in a plurality of neighboring ones of the memory cells, and sends an address in accordance with a result of the check, and a data correction circuit which corrects a value of data at the address that is sent, and sends the corrected value to the semiconductor memory.
    Type: Application
    Filed: August 11, 2011
    Publication date: December 1, 2011
    Inventor: Hiroshi SUKEGAWA
  • Biometric determination of group membership of recognized individuals
    Patent number: 8064651
    Abstract: A person identification device obtains information including biometric information of a person, detects the biometric information of at least one person from the obtained information, collates each detected biometric information with the biometric information of at least one registrant associated with group information and stored in a storage unit to thereby identify the person having the biometric information detected from the obtained information, classifies a plurality of successively identified persons into group candidates based on predetermined conditions, divides the persons of the group candidates into groups based on the group information of each person stored in the storage unit, and outputs a grouping result to an external device.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: November 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Sukegawa, Makoto Shimizu
  • MEMORY CHIP, INFORMATION STORING SYSTEM, AND READING DEVICE
    Publication number: 20110246791
    Abstract: According to one embodiment, a memory chip, which is connected to a writing device that writes data and to a reading device that reads data, includes: a memory including a first area that is a predetermined data storage area; a second encryption key generating unit that receives second key information stored in the reading device and generates a third key; and a sending unit that transmits, to the reading device, second encrypted data obtained by encrypting data stored in the memory using the third key. The second encrypted data is received by the reading device and is decrypted by using a fourth key that is stored in the reading device and that corresponds to the third key.
    Type: Application
    Filed: September 13, 2010
    Publication date: October 6, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toru Kambayashi, Taku Kato, Hiroshi Sukegawa, Yoshihiko Hirose, Koichi Fujisaki
  • MEMORY CONTROLLER, MEMORY SYSTEM, PERSONAL COMPUTER, AND METHOD OF CONTROLLING MEMORY SYSTEM
    Publication number: 20110238890
    Abstract: According to one embodiment, a memory controller that performs control of a nonvolatile semiconductor memory includes a first management table that stores correspondence between logical block addresses and physical block addresses, a second management table that stores a number of times of data writing for each of the logical block addresses, and a third management table that stores a number of times of data erasing for each of the physical block addresses. The memory controller according to the embodiment includes a writing control unit that selects a spare block not associated with the logical block address and writes data in the spare block. The writing control unit levels, based on the number of times of data writing associated with the logical block addresses and the number of times of data erasing associated with the physical block addresses, numbers of times of data erasing among the blocks.
    Type: Application
    Filed: September 20, 2010
    Publication date: September 29, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi SUKEGAWA
  • Memory device including memory controller
    Patent number: 8028206
    Abstract: A memory device includes a semiconductor memory including a plurality of memory cells, and a controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and are to be stored in a plurality of neighboring ones of the memory cells, and sends an address in accordance with a result of the check, and a data correction circuit which corrects a value of data at the address that is sent, and sends the corrected value to the semiconductor memory.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: September 27, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Sukegawa
  • Data remaining period management device and method
    Patent number: 8000927
    Abstract: A remaining period management device according to an example of the invention includes a statistic calculation unit that measures sampling data associated with monitoring target data stored in a storage device having a finite data remaining period and calculates sampling statistical data based on a measurement result of the sampling data. The device also includes a remaining period detection unit that obtains remaining period data indicative of a data remaining period of the monitoring target data based on predetermined remaining period characteristic data indicative of a characteristic that statistical data varies with elapse of data remaining period and the sampling statistical data calculated by the statistic calculation unit.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: August 16, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Sukegawa
  • MEMORY CHIP
    Publication number: 20110131470
    Abstract: According to one embodiment, a memory chip, which is connected to a controller that controls reading and writing of data in response to a request from an external device, includes: a memory including a special area that is a predetermined data storage area; a key storage unit that stores therein a second key that corresponds to a first key used by the external device to convert the data; a converting unit that receives, from the controller, data to be written into the special area and generates converted data by converting the data to be written using the second key; and a writing unit that writes the converted data into the special area.
    Type: Application
    Filed: September 15, 2010
    Publication date: June 2, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toru KAMBAYASHI, Akihiro KASAHARA, Shinichi MATSUKAWA, Hiroyuki SAKAMOTO, Taku KATO, Hiroshi SUKEGAWA, Yoshihiko HIROSE, Atsushi SHIMBO, Koichi FUJISAKI
  • NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM
    Publication number: 20110082968
    Abstract: A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device.
    Type: Application
    Filed: October 8, 2010
    Publication date: April 7, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasuo KUDO, Hiroshi Sukegawa, Kazuya Kawamoto
  • IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD
    Publication number: 20110074970
    Abstract: According to one embodiment, an image processing apparatus comprises a plurality of image input modules configured to input images, a detection module configured to detect object regions from an image input by any image input module, a feature extracting module configured to extract feature values from any object regions detected by the detecting module, and a control module configured to control processes the detection module and feature extracting module perform on the images input by the plurality of image input modules, in accordance with the result of detection performed by the detection module.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 31, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi Sukegawa
  • NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM
    Publication number: 20110055466
    Abstract: A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device.
    Type: Application
    Filed: November 8, 2010
    Publication date: March 3, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasuo KUDO, Hiroshi Sukegawa, Kazuya Kawamoto
  • Memory card and semiconductor device
    Patent number: 7890732
    Abstract: A memory card includes a controller and a nonvolatile semiconductor memory. The controller manages a correspondence between a first address in a semiconductor memory of a first erase block size and a second address in a semiconductor memory of a second erase block size other than the first erase block size. The nonvolatile semiconductor memory is a memory of the second erase block size. The controller executes access to the nonvolatile semiconductor memory by the second address.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: February 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Sukegawa
  • Nonvolatile semiconductor memory device
    Patent number: 7881106
    Abstract: A nonvolatile semiconductor memory device includes a nonvolatile memory including a first area which stores data for every n bits (n is a natural number of not less than 2), and a second area which stores data for every 1 bit, each of the first area and the second area including a plurality of memory cells each configured to store n-bit data on the basis of a threshold voltage, and a controller which sets 2n threshold voltages corresponding to n bits when writing n-bit data to a first memory cell included in the first area, and executes the n-bit data write operation when writing 1-bit data to a second memory cell included in the second area.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: February 1, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Sukegawa
  • Memory system
    Patent number: RE42398
    Abstract: In a memory system using a removable recording medium and data stored in the recording medium, identifying information for identifying each recording medium from others is held in the recording medium, and when data stored in the recording medium is used, the identifying information of the recording medium is required. As a result, when a flash memory card, etc. is used, a copyright is reliably protected.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: May 24, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki Tanaka, Hiroshi Nakamura, Hiroshi Sukegawa, Mikito Nakabayashi, Kazuya Kawamoto