Abstract: A data writing method is disclosed. In a memory system comprising a NAND flash memory and a controller which controls the memory, the memory system storing data provided from a host to the NAND flash memory, the data writing method comprises a steps of specifying a column address in which a column failure which has occurred in the NAND flash memory by the controller, and a step of, during writing into the NAND flash memory, writing data of a first logic level into a memory cell which corresponds to the specified column address regardless of write data provided from the controller.

Abstract: A memory controller for writing data in a first semiconductor memory including a plurality of memory cells having series-connected current paths and charge storage layers includes a host interface which configured to be receivable of first data from a host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with the state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes the first and second data in the first semiconductor memory. When writing the second data, the arithmetic unit does not select a word line adjacent to a select gate line, and selects a word line not adjacent to the select gate line.

Abstract: A memory system includes a nonvolatile memory including a plurality of memory cells, each memory cell being configured to store n levels (n is a natural number of not less than 3) in accordance with a threshold voltage, and a converter which encodes input data in the form of a bit string, records the encoded data in the nonvolatile memory, and limits a difference between levels which adjacent memory cells can take to not more than a predetermined level lower than the n levels.

Abstract: A memory system includes a memory which asserts a high-power-consumption operation output when an amount of the power consumption is high in internal operations in respective operations, and a controller which has an interface function between a host and the memory and receives the high-power-consumption operation output. The controller switches an operation mode thereof to a low power consumption mode when the high-power-consumption operation output is asserted.

Abstract: A nonvolatile semiconductor memory device includes a nonvolatile memory including a first area which stores data for every n bits (n is a natural number of not less than 2), and a second area which stores data for every 1 bit, each of the first area and the second area including a plurality of memory cells each configured to store n-bit data on the basis of a threshold voltage, and a controller which sets 2n threshold voltages corresponding to n bits when writing n-bit data to a first memory cell included in the first area, and executes the n-bit data write operation when writing 1-bit data to a second memory cell included in the second area.

Abstract: In a memory cell array, a plurality of memory cells each of which stores a plurality of bits are connected to a plurality of word lines and a plurality of bit lines and are arranged in a matrix. Control portions read a threshold level of a second memory cell adjacent to a first memory cell in the memory cell array, determine a correction level according to the threshold level read from the second memory cell, add the determined correction level to a read level of the first memory cell, and then read the threshold level of the first memory cell. A storage portion stores the correction level.

Abstract: An ECC control apparatus is to be connected between a host and a memory. The apparatus comprises a first input/output circuit, a detecting circuit, a code-generating circuit, a code-inserting circuit, a second input/output circuit. The first input/output circuit inputs and outputs data to and from the host. The detecting circuit detects a protected-data region and a redundant region of write data input to the first input/output circuit and having a predetermined data length. The code-generating circuit generates an error-correction code for correcting errors in data stored in the protected-data region. The code-inserting circuit inserts the error-correction code in the redundant region. The second input/output circuit inputs and outputs data to and from the memory.

Abstract: A face authentication apparatus includes a high tone image acquiring section, a tone converting section, a face characteristic extracting section and a face collation section. The high tone image acquiring section acquires a high tone image containing the face of a walker. The tone converting section converts the acquired high tone image to a low tone image by tone conversion processing which optimizes the brightness of a face area in the high tone image acquired by the high tone image acquiring section. The face characteristic extracting section executes an extraction processing for the face characteristic information based on the low tone image whose brightness is optimized by the tone converting section. Further, the face collation section executes face collation processing based on the low tone image whose brightness is optimized by the tone converting section.

Abstract: The image input apparatus performs detection of a facial area of a person based on an input image. The image input apparatus compiles information of a position where the facial area is detected within a specified time and manages as a map. From the map, the image input apparatus specifies the area where the instability of the person facial area detection occurs, namely, the area where there is a case that the facial area is not detected among the areas where a facial area is normally to be detected. The image input apparatus controls adjustment factors of a camera so that accurate detection of the facial area is performed at the specified area.

Abstract: A processor boot-up controller includes: a volatile memory connected to a nonvolatile memory; a selector, which transfers boot-up codes to the volatile memory from the nonvolatile memory; a controller for the nonvolatile memory configured from a boot-up control sequencer, which transmits CPU read-in data to the CPU and brings the CPU into a wait state until boot-up code transfer completes; and an error detection and correction unit connected to the external CPU and the nonvolatile memory. The processor boot-up controls the CPU by reading data from the nonvolatile memory. The processor enables the CPU to access a SRAM in the shortest time in sync with the SRAM's ready timing, resulting in a reduction of average system boot-up time. An information processing system can use the controller for example for a nonvolatile memory, a microprocessor boot-up controller, and multi-valued nonvolatile memory.

Abstract: When authentication data of a person O to be authenticated is registered as dictionary data, this authentication data of the person to be authenticated is acquired and collated with the registered dictionary data. In accordance with the collation result, the dictionary data is updated.

Abstract: A remaining period management device according to an example of the invention comprises a statistic calculation unit that measures sampling data associated with monitoring target data stored in a storage device having a finite data remaining period and calculates sampling statistical data based on a measurement result of the sampling data, and a remaining period detection unit that obtains remaining period data indicative of a data remaining period of the monitoring target data based on predetermined remaining period characteristic data indicative of a characteristic that statistical data varies with elapse of data remaining period and the sampling statistical data calculated by the statistic calculation unit.

Abstract: A memory device includes a semiconductor memory including a plurality of memory cells, and a controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and are to be stored in a plurality of neighboring ones of the memory cells, and sends an address in accordance with a result of the check, and a data correction circuit which corrects a value of data at the address that is sent, and sends the corrected value to the semiconductor memory.

Abstract: This non-volatile memory system includes: a non-volatile memory; and a memory controller controlling read and write of the non-volatile memory. Access control of the non-volatile memory system is performed in accordance with a logical address, using an address translation table within the memory controller that is updated in association with data write and that indicates a correlation between logical addresses provided by a host and physical addresses of the non-volatile memory. The non-volatile memory system is also configured to be able to set a system configuration and function in relation to the host.

Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.

Abstract: A memory system includes a ferroelectric memory formed by arranging a plurality of memory cells having a ferroelectric capacitor and cell transistor, a flash EEPROM formed by arranging a plurality of memory cells having a floating gate and capable of electrically erasing and writing data, a control circuit configured to control the ferroelectric memory and flash EEPROM, and an interface circuit configured to communicate with the outside. The flash EEPROM stores data. The ferroelectric memory stores at least one of root information for storing the data, directory information, the file name of the data, the file size of the data, file allocation table information storing the storage location of the data, and the write completion time of the data.

Abstract: A plurality of memory cells each storing n values (n is a natural number which is not smaller than 3) are arranged in a matrix form in a memory cell array, and each memory cell is connected with a word line and a bit line. Each memory cell stores the n-valued data by a first write operation and a second write operation. A read section sets a potential of a word line, and reads data from a memory cell in the memory cell array. If data read by the read section and written in the second write operation includes an uncorrectable error, a control section changes a potential of a word line supplied to the read section when reading data written in the first write operation.

Abstract: A data writing method is disclosed. In a memory system comprising a NAND flash memory and a controller which controls the memory, the memory system storing data provided from a host to the NAND flash memory, the data writing method comprises a steps of specifying a column address in which a column failure which has occurred in the NAND flash memory by the controller, and a step of, during writing into the NAND flash memory, writing data of a first logic level into a memory cell which corresponds to the specified column address regardless of write data provided from the controller.

Abstract: A semiconductor device includes an interface which executes an interfacing process with a semiconductor memory, and a circuit which performs control to write serial data to the semiconductor memory while skipping a position of a defective column on the semiconductor memory.

Abstract: A first face detecting section detects the face of a passerby based on an image obtained from a first camera set to be easily recognized by the passerby. A second face detecting section detects the face of the passerby based on an image obtained from a second camera set so that the camera will be difficult to be recognized by the passerby. A classifying section classifies the passerby based on the detection results of the faces by the first and second face detecting sections and adjusts a threshold value for authentication based on the classification result. The face collating section calculates the similarity between the face of the passerby and each of faces of registrants and determines whether the passerby is a registrant or not according to whether the degree of calculated similarity is not lower than the adjusted threshold value for authentication.