Patents by Inventor Hiroshi Sunamura
Hiroshi Sunamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10056405Abstract: In the case where a signal delay is found in a circuit operation in a semiconductor chip, when a repeater for delay reduction is additionally formed as a result of a design change, an increase in the area of the semiconductor chip and an increase in the manufacturing cost of a semiconductor device are prevented. The inverter forming the repeater is formed of transistors formed in the upper portion of stacked wiring layers, not transistors in the vicinity of a main surface of a semiconductor substrate. By thus implementing a design change such that the repeater is added, the number of the wiring layers which need a layout change is reduced.Type: GrantFiled: August 31, 2016Date of Patent: August 21, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Hiroshi Sunamura
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Patent number: 9680031Abstract: Provided is an in-wiring-layer active element (component) which allows for electrical isolation between a gate electrode and a channel in a top gate structure. A semiconductor device includes a first wiring layer, a second wiring layer, and a semiconductor element. The first wiring layer has a first interlayer insulating layer, and a first wire embedded in the first interlayer insulating layer. The second wiring layer has a second interlayer insulating layer, and second wires embedded in the second interlayer insulating layer. The semiconductor element is provided at least in the second wiring layer. The semiconductor element includes a semiconductor layer provided in the second wiring layer, a gate insulating film provided in contact with the semiconductor layer, a gate electrode provided on the opposite side of the semiconductor layer via the first gate insulating film, and a first side wall film provided over a side surface of the semiconductor layer.Type: GrantFiled: February 24, 2016Date of Patent: June 13, 2017Assignee: Renesas Electronics CorporationInventors: Hiroshi Sunamura, Kishou Kaneko, Yoshihiro Hayashi
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Publication number: 20170098662Abstract: In the case where a signal delay is found in a circuit operation in a semiconductor chip, when a repeater for delay reduction is additionally formed as a result of a design change, an increase in the area of the semiconductor chip and an increase in the manufacturing cost of a semiconductor device are prevented. The inverter forming the repeater is formed of transistors formed in the upper portion of stacked wiring layers, not transistors in the vicinity of a main surface of a semiconductor substrate. By thus implementing a design change such that the repeater is added, the number of the wiring layers which need a layout change is reduced.Type: ApplicationFiled: August 31, 2016Publication date: April 6, 2017Inventor: Hiroshi SUNAMURA
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Patent number: 9577062Abstract: A gate conductor material stack including, from bottom to top, of a first metallic nitride, a second metallic nitride, and a conductive material portion is employed for a transistor in combination with a gate dielectric including a high dielectric constant (high-k) dielectric material. The second metallic nitride includes a nitride of an aluminum-containing metallic alloy of at least two elemental metals, and can be selected from TaAlN, TiAlN, and WAlN. The second metallic nitride can provide a function of oxygen scavenging from the high-k gate dielectric and/or prevent diffusion of atoms from the conductive material portion. The gate conductor material stack can enable a reduced inversion thickness and/or a reduced magnitude for a linear threshold voltage for p-type field effect transistors compared with a gate electrode employing a single metallic material.Type: GrantFiled: October 27, 2014Date of Patent: February 21, 2017Assignees: International Business Machines Corporation, Renesas Electronics CorporationInventors: Hemanth Jagannathan, Hiroshi Sunamura
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Patent number: 9496403Abstract: A circuit including an inverter is provided for a wiring layer. A semiconductor device is provided with a wiring layer circuit which is formed over an insulating film and includes at least one inverter element. The inverter is provided with a first transistor element and a resistance element which is connected to the first transistor via a connection node. The first transistor element is provided with a gate electrode which is embedded in an interlayer insulating film including the insulating film, a gate insulating film which is formed over the interlayer insulating film and the gate electrode, and a first semiconductor layer which is formed over the gate insulating film between a source electrode and a drain electrode. The resistance element is provided with a second semiconductor layer which functions as a resistance. The first semiconductor layer and the second semiconductor layer are formed in the same layer.Type: GrantFiled: December 10, 2012Date of Patent: November 15, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kishou Kaneko, Hiroshi Sunamura, Yoshihiro Hayashi
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Publication number: 20160240564Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.Type: ApplicationFiled: April 27, 2016Publication date: August 18, 2016Inventors: Hiroshi SUNAMURA, Kishou KANEKO, Naoya FURUTAKE, Shinobu SAITOU, Yoshihiro HAYASHI
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Publication number: 20160172504Abstract: Provided is an in-wiring-layer active element (component) which allows for electrical isolation between a gate electrode and a channel in a top gate structure. A semiconductor device includes a first wiring layer, a second wiring layer, and a semiconductor element. The first wiring layer has a first interlayer insulating layer, and a first wire embedded in the first interlayer insulating layer. The second wiring layer has a second interlayer insulating layer, and second wires embedded in the second interlayer insulating layer. The semiconductor element is provided at least in the second wiring layer. The semiconductor element includes a semiconductor layer provided in the second wiring layer, a gate insulating film provided in contact with the semiconductor layer, a gate electrode provided on the opposite side of the semiconductor layer via the first gate insulating film, and a first side wall film provided over a side surface of the semiconductor layer.Type: ApplicationFiled: February 24, 2016Publication date: June 16, 2016Inventors: Hiroshi Sunamura, Kishou Kaneko, Yoshihiro Hayashi
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Patent number: 9368403Abstract: The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire.Type: GrantFiled: March 25, 2015Date of Patent: June 14, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroshi Sunamura, Naoya Inoue, Kishou Kaneko
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Patent number: 9356026Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.Type: GrantFiled: October 6, 2015Date of Patent: May 31, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroshi Sunamura, Kishou Kaneko, Naoya Furutake, Shinobu Saitou, Yoshihiro Hayashi
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Publication number: 20160148845Abstract: A semiconductor device is provided which includes an N-type semiconductor layer and a P-type semiconductor layer coexisting in the same wiring layer without influences on the properties of a semiconductor layer. The semiconductor device includes a first wiring layer with a first wiring, a second wiring layer with a second wiring, and first and second transistors provided in the first and second wiring layers. The first transistor includes a first gate electrode, a first gate insulating film, a first oxide semiconductor layer, a first hard mask layer, and first insulating sidewall films covering the sides of the first oxide semiconductor layer. The second transistor includes a second gate electrode, a second gate insulating film, a second oxide semiconductor layer, and a second hard mask layer.Type: ApplicationFiled: November 24, 2015Publication date: May 26, 2016Inventors: Hiroshi Sunamura, Kishou Kaneko, Naoya Furutake, Shinobu Saitou, Yoshihiro Hayashi
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Patent number: 9331071Abstract: Provided is an in-wiring-layer active element (component) which allows for electrical isolation between a gate electrode and a channel in a top gate structure. A semiconductor device includes a first wiring layer, a second wiring layer, and a semiconductor element. The first wiring layer has a first interlayer insulating layer, and a first wire embedded in the first interlayer insulating layer. The second wiring layer has a second interlayer insulating layer, and second wires embedded in the second interlayer insulating layer. The semiconductor element is provided at least in the second wiring layer. The semiconductor element includes a semiconductor layer provided in the second wiring layer, a gate insulating film provided in contact with the semiconductor layer, a gate electrode provided on the opposite side of the semiconductor layer via the first gate insulating film, and a first side wall film provided over a side surface of the semiconductor layer.Type: GrantFiled: August 22, 2013Date of Patent: May 3, 2016Assignee: Renesas Electronics CorporationInventors: Hiroshi Sunamura, Kishou Kaneko, Yoshihiro Hayashi
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Publication number: 20160118470Abstract: A gate conductor material stack including, from bottom to top, of a first metallic nitride, a second metallic nitride, and a conductive material portion is employed for a transistor in combination with a gate dielectric including a high dielectric constant (high-k) dielectric material. The second metallic nitride includes a nitride of an aluminum-containing metallic alloy of at least two elemental metals, and can be selected from TaAlN, TiAlN, and WAlN. The second metallic nitride can provide a function of oxygen scavenging from the high-k gate dielectric and/or prevent diffusion of atoms from the conductive material portion. The gate conductor material stack can enable a reduced inversion thickness and/or a reduced magnitude for a linear threshold voltage for p-type field effect transistors compared with a gate electrode employing a single metallic material.Type: ApplicationFiled: October 27, 2014Publication date: April 28, 2016Inventors: Hemanth Jagannathan, Hiroshi Sunamura
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Patent number: 9293455Abstract: Provided is an in-wiring-layer active element (component) which allows for electrical isolation between a gate electrode and a channel in a top gate structure. A semiconductor device includes a first wiring layer, a second wiring layer, and a semiconductor element. The first wiring layer has a first interlayer insulating layer, and a first wire embedded in the first interlayer insulating layer. The second wiring layer has a second interlayer insulating layer, and second wires embedded in the second interlayer insulating layer. The semiconductor element is provided at least in the second wiring layer. The semiconductor element includes a semiconductor layer provided in the second wiring layer, a gate insulating film provided in contact with the semiconductor layer, a gate electrode provided on the opposite side of the semiconductor layer via the first gate insulating film, and a first side wall film provided over a side surface of the semiconductor layer.Type: GrantFiled: August 22, 2013Date of Patent: March 22, 2016Assignee: Renesas Electronics CorporationInventors: Hiroshi Sunamura, Kishou Kaneko, Yoshihiro Hayashi
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Publication number: 20160043006Abstract: The present invention makes it possible to increase the selectivity of a gate insulation film in an active element formed in a wiring layer. A semiconductor device according to the present invention has a bottom gate type transistor using an antireflection film formed over an Al wire in a wiring layer as a gate wire.Type: ApplicationFiled: October 14, 2015Publication date: February 11, 2016Inventors: Kishou KANEKO, Hiroshi SUNAMURA, Yoshihiro HAYASHI
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Publication number: 20160027925Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.Type: ApplicationFiled: October 6, 2015Publication date: January 28, 2016Inventors: Hiroshi SUNAMURA, Kishou KANEKO, Naoya FURUTAKE, Shinobu SAITOU, Yoshihiro HAYASHI
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Patent number: 9230865Abstract: A semiconductor device is provided which includes an N-type semiconductor layer and a P-type semiconductor layer coexisting in the same wiring layer without influences on the properties of a semiconductor layer. The semiconductor device includes a first wiring layer with a first wiring, a second wiring layer with a second wiring, and first and second transistors provided in the first and second wiring layers. The first transistor includes a first gate electrode, a first gate insulating film, a first oxide semiconductor layer, a first hard mask layer, and first insulating sidewall films covering the sides of the first oxide semiconductor layer. The second transistor includes a second gate electrode, a second gate insulating film, a second oxide semiconductor layer, and a second hard mask layer.Type: GrantFiled: May 12, 2015Date of Patent: January 5, 2016Assignee: Renesas Electronics CorporationInventors: Hiroshi Sunamura, Kishou Kaneko, Naoya Furutake, Shinobu Saitou, Yoshihiro Hayashi
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Publication number: 20150349134Abstract: There is provided a readily manufacturable semiconductor device including two transistors having mutually different characteristics. The semiconductor device includes a substrate, a multilayer wiring layer disposed over the substrate, a first transistor disposed in the multilayer wiring layer, and a second transistor disposed in a layer different from a layer including the first transistor disposed therein of the multilayer wiring layer, and having different characteristics from those of the first transistor. This can provide a readily manufacturable semiconductor device including two transistors having mutually different characteristics.Type: ApplicationFiled: August 10, 2015Publication date: December 3, 2015Inventors: Hiroshi SUNAMURA, Naoya INOUE, Kishou Kaneko
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Patent number: 9190475Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.Type: GrantFiled: September 13, 2013Date of Patent: November 17, 2015Assignee: Renesas Electronics CorporationInventors: Hiroshi Sunamura, Kishou Kaneko, Naoya Furutake, Shinobu Saitou, Yoshihiro Hayashi
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Patent number: 9166057Abstract: The present invention makes it possible to increase the selectivity of a gate insulation film in an active element formed in a wiring layer. A semiconductor device according to the present invention has a bottom gate type transistor using an antireflection film formed over an Al wire in a wiring layer as a gate wire.Type: GrantFiled: December 23, 2013Date of Patent: October 20, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kishou Kaneko, Hiroshi Sunamura, Yoshihiro Hayashi
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Patent number: 9153588Abstract: There is provided a readily manufacturable semiconductor device including two transistors having mutually different characteristics. The semiconductor device includes a substrate, a multilayer wiring layer disposed over the substrate, a first transistor disposed in the multilayer wiring layer, and a second transistor disposed in a layer different from a layer including the first transistor disposed therein of the multilayer wiring layer, and having different characteristics from those of the first transistor. This can provide a readily manufacturable semiconductor device including two transistors having mutually different characteristics.Type: GrantFiled: January 10, 2013Date of Patent: October 6, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroshi Sunamura, Naoya Inoue, Kishou Kaneko